Self-Aligned Cross-Point Memory Fabrication

Abstract

Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections.

1 . A method for fabricating a cross-point memory element, comprising:
 patterning a multi-layered structure forming a plurality of first channels and a plurality of first gratings, the multi-layered structure having a first conducting layer and a switching material stack layer;   depositing a first dielectric material layer on the multi-layered structure filling the first channels;   providing a crown surface defined by exposed surfaces of the gratings and surfaces of dielectric material;   depositing an upper conducting layer on the crown surface;   patterning the upper conducting layer forming a plurality of second channels and a plurality of second gratings, the second channels positioned substantially orthogonal to the first channels;   depositing a second dielectric material layer filling the second channels;   wherein orthogonal overlapping of the first conducting layer and the upper conducting layer provide a connection via the switching material stack layer forming a memory element.   
     
     
         2 . The method of  claim 1 , wherein the multi-layered structure includes:
 a substrate layer;   the first conducting layer; and,   the switching material stack layer   wherein patterning the multi-layered structure includes etching the first conducting layer and the switching material stack layer to form the first channels.   
     
     
         3 . The method of  claim 2 , wherein the first conducting layer is formed of tungsten. 
     
     
         4 . The method of  claim 2 , wherein the first channels are a series of substantially parallel channels defining gratings. 
     
     
         5 . The method of  claim 2 , wherein the first channels are formed using a first lithography step followed by an etching step that stops before the substrate layer. 
     
     
         6 . The method of  claim 2 , wherein the upper conducting layer and the first conducting layer are formed of tungsten. 
     
     
         7 . The method of  claim 1 , wherein patterning the upper conducting layer includes a lithography step and an etching step. 
     
     
         8 . The method of  claim 1 , wherein patterning the multi-layered structure includes an imprint lithography process. 
     
     
         9 . The method of  claim 1 , wherein patterning the upper conducting layer includes an imprint lithography process. 
     
     
         10 . A method for fabricating a cross-point memory element for a memory array comprising:
 applying a first lithography step to a composite multilayer structure that includes a substrate and a first resist material layer whereby a pattern for a plurality of first channels is formed in the first resist material layer;   applying a sequence of deposition steps to fill the plurality of first channels with a first dielectric material layer;   depositing a second resist material layer on the dielectric material; providing a modified composite multilayer structure;   applying a second lithography step to the modified composite multilayer structure whereby a pattern for a plurality of second channels, disposed over and orthogonal to the plurality of first channels, is formed in the second resist material; and,   applying a sequence of deposition steps to fill the plurality of second channels with a second dielectric material layer.   
     
     
         11 . The method of  claim 10 , wherein the composite multilayer structure includes:
 a substrate;   a first conducting layer; and,   a switching material stack layer.   
     
     
         12 . The method of  claim 10 , further comprising planarizing the first dielectric material layer. 
     
     
         13 . The method of  claim 10 , wherein the modified composite multilayer structure includes a second conducting layer. 
     
     
         14 . The method of  claim 10 , wherein the first lithography step is an imprint lithography process. 
     
     
         15 . The method of  claim 10 , wherein the first channels are substantially orthogonal to the second channels. 
     
     
         16 . The method of  claim 15 , wherein orthogonal overlapping provides a connection forming a memory element via a switching material layer in the first resist material layer 
     
     
         17 . The method of  claim 10 , wherein the first resist material layer and the second resist material layer include tungsten. 
     
     
         18 . A method for fabricating a cross-point memory element, comprising:
 patterning a multi-layered structure forming a plurality of first channels;   depositing a first dielectric material layer on the multi-layered structure filling the first channels;   providing a crown surface on the multi-layered structure;   depositing an upper conducting layer on the crown surface;   patterning the upper conducting layer forming a plurality of second channels, the second channels positioned substantially orthogonal to the first channels; and,   depositing a second dielectric material layer filling the second channels.   
     
     
         19 . The method of  claim 18 , wherein the multi-layered structure includes:
 a substrate layer;   a first conducting layer; and,   a switching material layer.   
     
     
         20 . The method of  claim 19 , wherein orthogonal overlapping of the first conducting layer and the upper conducting layer forms a memory element via the switching material layer.