Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

Abstract

A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

1 . A package-on-package apparatus comprising:
 a package substrate including a die side and a land side;   a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height; and   an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height.   
     
     
         2 . The apparatus of  claim 1 , wherein the interposer has a ball-grid array, the apparatus further including:
 a top package, wherein the top package includes at least one microelectronic device, and wherein the top package mates to the interposer ball-grid array.   
     
     
         3 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side; and   the top chip is a wire-bond chip disposed on the flip chip.   
     
     
         4 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a wire-bond second chip disposed above the flip chip; and   the top chip is a wire-bond subsequent chip disposed above the wire-bond second chip.   
     
     
         5 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a through-silicon via (TSV) second chip disposed on the flip chip; and   the top chip is a wire-bond subsequent chip disposed on the TSV second chip.   
     
     
         6 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a through-silicon via (TSV) second chip disposed on the flip chip;   a TSV third chip disposed on the TSV second chip; and   the top chip is a wire-bond fourth chip disposed on the TSV third chip.   
     
     
         7 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a through-silicon via (TSV) second chip disposed on the flip chip;   a TSV third chip disposed on the TSV second chip, wherein the TSV third chip is a plurality of TSV chips in a range from 2 to 8 TSV chips; and   the top chip is a wire-bond subsequent chip disposed above the TSV third chip.   
     
     
         8 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a through-silicon via (TSV) second chip disposed on the flip chip;   a TSV third chip disposed above the TSV second chip;   a wire-bond fourth chip disposed above the TSV second chip; and   the top chip is a wire-bond subsequent chip disposed above the wire-bond fourth chip.   
     
     
         9 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a wire-bond second chip disposed above the TSV first chip;   a through-silicon via (TSV) third chip disposed above the wire-bond second chip; and   the top chip is a wire-bond subsequent chip disposed above the TSV third chip.   
     
     
         11 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side; and   the top chip is a through-silicon via (TSV) chip disposed on the flip chip.   
     
     
         12 . The apparatus of  claim 1 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   the top chip is a through-silicon via (TSV) subsequent chip disposed above the flip chip; and   at least one TSV chip disposed between the bottom chip and the top chip in a range from 2 to 7.   
     
     
         13 . A package-on-package stacked-chip apparatus comprising:
 a package substrate including a die side and a land side;   a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height;   an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height; and   a top package disposed on the interposer, wherein the top package includes at least one microelectronic device.   
     
     
         14 . The apparatus of  claim 13 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side; and   the top chip is a through-silicon via (TSV) chip disposed on the flip chip.   
     
     
         15 . The apparatus of  claim 13 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   the top chip is a through-silicon via (TSV) subsequent chip disposed above the flip chip; and   at least one TSV chip disposed between the bottom chip and the top chip in a range from 2 to 7.   
     
     
         16 . The apparatus of  claim 13 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side; and   the top chip is a wire-bond chip disposed on the flip chip.   
     
     
         17 . The apparatus of  claim 13 , wherein the chip stack includes:
 the bottom chip is a flip chip mounted on the substrate die side;   a wire-bond second chip disposed on the flip chip; and   the top chip is a wire-bond subsequent chip disposed above the wire-bond second chip.   
     
     
         18 . A method of assembling a package-on-package stacked-chip apparatus, comprising:
 assembling a top package with a ball-grid array to a matching ball-grid array of a 3-dimensional (3D) stacked-chip apparatus, the 3D stacked-chip apparatus including:
 a package substrate including a land side and a die side; 
 a chip stack disposed on the die side, wherein the chip stack has a stack height; and 
 an interposer including a die side and a top side, wherein the interposer produces an offset height that matches the stack height, and wherein assembling includes mating the top package to the interposer. 
   
     
     
         19 . The method of  claim 18 , wherein the chip stack is assembled on the package substrate before assembling the interposer to the package substrate. 
     
     
         20 . The method of  claim 18 , wherein the interposer is assembled on the package substrate before assembling the chip stack to the package substrate. 
     
     
         21 . The method of  claim 18 , further including forming a stack encapsulation over the chip stack. 
     
     
         22 . The method of  claim 18 , wherein the chip stack is formed including:
 flip-chip mounting a bottom chip on the substrate die side; and   wire-bond mounting a top chip above the flip chip.   
     
     
         23 . The method of  claim 18 , wherein the chip stack is formed including:
 flip-chip mounting a bottom chip on the substrate die side;   wire-bond mounting a second chip above the bottom chip; and   wire-bond mounting a top chip above the second chip.   
     
     
         24 . The apparatus of  claim 18 , wherein the chip stack is formed including:
 flip chip-mounting a bottom chip on the substrate die side;   through-silicon via (TSV) mounting a second chip on the flip chip; and   wire-bond mounting a subsequent chip as a top chip above the second chip.   
     
     
         25 . A computing system, comprising:
 a package substrate including a die side and a land side;   a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the top chip is supported by the bottom chip, and wherein the chip stack has an offset height;   an interposer disposed on the die side and surrounding the chip stack, wherein the interposer matches the offset height; and   a top package disposed on the interposer, wherein the top package includes at least one microelectronic device; and   a device housing that contains the top package.   
     
     
         26 . The computing system of  claim 25 , wherein the computing system is part of one of a cellular telephone, a pager, a portable computer, a desktop computer, and a two-way radio.