Method of manufacturing semiconductor integrated circuit devcie having capacitor element

Abstract

In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

1 . A one-chip microcomputer comprising:
 a semiconductor substrate including a memory cell formed on a memory cell forming region of the substrate,   the memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed over the memory cell forming region and a source region and a drain region formed in the substrate,   the first n-channel MISFET being arranged in a first direction adjacent to the first p-channel MISFET such that the gate electrode of the first n-channel MISFET is integrally formed with the gate electrode of the first p-channel MISFET by a first common gate electrode extending in the first direction,   the second n-channel MISFET being arranged in the first direction adjacent to the second p-channel MISFET such that the gate electrode of the second n-channel MISFET is integrally formed with the gate electrode of the second p-channel MISFET by a second common gate electrode extending in the first direction;   a further MISFET formed in a circuit element forming region of the substrate, the further MISFET having a gate electrode formed over the circuit element forming region and semiconductor regions formed in the substrate,   the semiconductor regions serving as a source region and a drain region of the further MISFET;   a first insulating film including silicon and nitrogen and formed so as to cover the first common gate electrode and the second common gate electrode, the drain regions of the first and second n-channel MISFETs and the first and second p-channel MISFETs, and the further MISFET;   a second insulating film formed on the first insulating film so as to cover the first insulating film such that after planarizing a surface of the second insulating film, the second insulating film is etched by using the first insulating film as an etching stopper to form a first opening, a second opening and a third opening and such that the first insulating film within the openings is etched so as to expose the drain region of the second n-channel MISFET in the first opening, to expose the second common gate electrode and the drain region of the first p-channel MISFET in the second opening and   
       to expose a semiconductor region of the further MISFET in the third opening;
 a first conductive film formed in the first opening so as to electrically connect the drain region of the second n-channel MISFET; 
 a second conductive film formed in the second opening so as to electrically connect the second common gate electrode and the drain region of the first p-channel MISFET; and 
 a third conductive film formed in the third opening so as to electrically connect the semiconductor region of the further MISFET, 
 wherein the first common gate electrode, the drain region of the second n-channel MISFET, the drain region of the second p-channel MISFET and the first conductive film are electrically connected with each other by a first interconnection line, and 
 wherein the second common gate electrode, the drain region of the first n-channel MISFET, the drain region of the first p-channel MISFET and the second conductive film are electrically connected with each other by a second interconnection MISFET is integrally formed with the gate electrode of the second p-channel MISFET by a second common gate electrode extending in the first direction; 
 a first insulating film including silicon and nitrogen and formed so as to cover the first common gate electrode and the second common gate electrode, the drain regions of the first and second n-channel MISFETs and the first and second p-channel MISFETs; 
 a second insulating film formed on the first insulating film so as to cover the first insulating film such that after planarizing a surface of the second insulating film, the second insulating film is etched by using the first insulating film as an etching stopper to form a first opening, a second opening and a third opening and such that the first insulating film within the openings is etched so as to expose the drain region of the second n-channel MISFET in the first opening and to expose the second common gate electrode and the drain region of the first p-channel MISFET in the second opening; 
 a first conductive film filled in the first opening so as to electrically connect to the drain region of the second n-channel MISFET; 
 a second conductive film filled in the second opening so as to electrically connect the second common gate electrode and the drain region of the first p-channel MISFET; and 
 a first interconnection line electrically connected to the second common gate electrode, the drain region of the first n-channel MISFET, the drain region of the first p-channel MISFET and the second conductive film; 
 a second interconnection line electrically connected to the first common gate electrode, the drain region of the second n-channel MISFET, the drain region of the second p-channel MISFET, and the first conductive film. 
 
     
     
         2 . A semiconductor integrated circuit device according to  claim 1 , wherein the first insulating film is comprised of a silicon nitride film. 
     
     
         3 . A semiconductor integrated circuit device according to  claim 1 , wherein the first interconnection line is integrally formed with the first conductive film, and wherein the second interconnection line is integrally formed with the second conductive film. 
     
     
         4 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate including a memory cell formed on a memory cell forming region of the substrate,   the memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed over the memory cell forming region and a source region and a drain region formed in the substrate,   the first n-channel MISFET being arranged in a first direction adjacent to the first p-channel MISFET such that the gate electrode of the first n-channel MISFET is integrally formed with the gate electrode of the first p-channel MISFET by a first common gate electrode extending in the first direction,   the second n-channel MISFET being arranged in the first direction adjacent to the second p-channel MISFET such that the gate electrode of the second n-channel second p-channel MISFET and the first conductive film; and   a power voltage line and a reference voltage line formed over the second insulating film and over the first and the second interconnection lines,   the power voltage line and the reference voltage line extending in a second direction crossing to the first direction over the second insulating film and the first and the second interconnection lines.   
     
     
         5 . A semiconductor integrated circuit device according to  claim 4 , wherein the first insulating film is comprised of a silicon nitride film. 
     
     
         6 . A semiconductor integrated circuit device according to  claim 4 , wherein the memory cell is a memory cell of a static random access memory. 
     
     
         7 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate including a first n-channel MISFET, formed in a first region of the substrate, and a memory cell formed in a memory cell forming region of the substrate,   the first n-channel MISFET having a gate electrode formed over the first region and a source region and a drain region formed in the substrate,   the memory cell including a selecting MISFET and a capacitor element electrically coupled to the selecting MISFET,   the selecting MISFET having a gate electrode formed over the memory cell forming region and semiconductor regions formed in the substrate,   the semiconductor regions serving as a source region and a drain region of the selecting MISFET;   a first insulating film including silicon and nitrogen and formed so as to cover the gate electrodes and the drain regions of the first n-channel MISFET and the selecting MISFET;   a second insulating film formed on the first insulating film so as to cover the first insulating film such that after planarizing a surface of the second insulating film, the second insulating film is etched by using the first insulating film as an etching stopper to form a first opening, a second opening and a third opening and such that the first insulating film within the openings is etched so as to expose the drain region of the first n-channel MISFET in the first opening and to expose a semiconductor region of the selecting MISFET in the second opening;   a first conductive film formed in the first opening so as to electrically connect to the drain region of the second n-channel MISFET; and   a second conductive film formed in the second opening so as to electrically connect to the semiconductor region of the selecting MISFET.   
     
     
         8 . A semiconductor integrated circuit device according to  claim 7 , wherein the first insulating film is comprised of a silicon nitride film. 
     
     
         9 . A semiconductor integrated circuit device according to  claim 7 , wherein the memory cell is a memory cell of a dynamic random access memory. 
     
     
         10 . A semiconductor integrated circuit device according to  claim 7 , wherein the capacitor element is formed over the substrate. 
     
     
         11 . A semiconductor integrated circuit device according to  claim 7 , wherein the first conductive film and the second conductive film are filled in the first opening and the second opening, respectively, and
 wherein the first conductive film and the second conductive film are comprised of metal material.   
     
     
         12 . A semiconductor integrated circuit device according to  claim 7 , wherein the first conductive film and the second conductive film are comprised of metal material. 
     
     
         13 . A method of manufacturing a semiconductor integrated circuit device comprising steps of:
 (a) providing a semiconductor substrate with a first memory cell formed in a first memory cell forming region of the substrate and with a second memory cell formed in a second memory cell forming region of the substrate,   the first memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on the memory cell forming region and a source region and a drain region formed in the substrate,   the gate electrode of the first n-channel MISFET being integrally formed with the gate electrode of the first p-channel MISFET by a first common gate electrode,   the gate electrode of the second n-channel MISFET being integrally formed with the gate electrode of the second p-channel MISFET by a second common gate electrode,   the first memory cell including a selecting MISFET formed in a circuit element forming region;   (b) forming a first insulating film including silicon and nitrogen so as to cover the first common gate electrode and the second common gate electrode and the drain regions of the first and second n-channel MISFETs and the first and second p-channel MISFETs, and the selecting MISFET;   (c) forming a second insulating film on the first insulating film to cover the first insulating film;   (d) after planarizing a surface of the second insulating film, etching the second insulating film by using the first insulating film as an etching stopper to form a first opening, a second opening and a third opening, and etching the first insulating film within the openings to expose the first common gate electrode and the drain region of the second n-channel MISFET in the first opening, to expose the second common gate electrode and the drain region of the first p-channel MISFET in the second opening, and to expose a semiconductor region of the selecting MISFET in the third opening; and   (e) forming a first conductive film in the first opening to electrically connect the first common gate electrode to the drain region of the second n-channel MISFET, a second conductive film in the second opening to electrically connect to the second common gate electrode and the drain region of the first p-channel MISFET, and a third conductive film in the third opening to electrically connect to the semiconductor region of the selecting MISFET.   
     
     
         14 . A method of manufacturing a semiconductor integrated circuit device according to  claim 13 , wherein the first insulating film is comprised of a silicon nitride film. 
     
     
         15 . A method of manufacturing a semiconductor integrated circuit device according to  claim 13 , wherein the first memory cell is a memory cell of a static random access memory, and wherein the second memory cell is a memory cell of a dynamic random access memory. 
     
     
         16 . A method of manufacturing a semiconductor integrated circuit device according to  claim 13 , wherein the capacitor element is formed over the substrate. 
     
     
         17 . A method of manufacturing a semiconductor integrated circuit device according to  claim 13 , wherein the first conductive film, the second conductive film and the third conductive film are filled in the first opening, the second opening and the third opening, respectively, and
 wherein the first conductive film, the second conductive film and the third conductive film are comprised of metal material.   
     
     
         18 . A method of manufacturing a semiconductor integrated circuit device according to  claim 13 , wherein the first conductive film, the second conductive film and the third conductive film are comprised of metal material.