Semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material and methods of forming the same

Abstract

A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.

1 . A semiconductor device comprising:
 a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, the cell region including an active region defined by a device isolation layer, the peripheral circuit region including an active region defined by the device isolation layer, and the resistor region including the device isolation layer;   a cell gate structure disposed on the active region of the cell region, comprising a first insulating layer, a charge storage layer, a second insulating layer, and a cell gate pattern stacked sequentially;   a peripheral circuit gate structure disposed on the active region of the peripheral circuit region, comprising a third insulating layer and a peripheral circuit gate pattern stacked sequentially; and   a resistor structure disposed on the device isolation layer of the resistor region, comprising a resistor pattern;   wherein the cell gate pattern and the resistor pattern comprise a same material; and   wherein the peripheral circuit region and the resistor regions are spaced apart from the entire cell region, the cell region and the resistor region are spaced apart from the entire peripheral circuit region, and the cell region and the peripheral circuit region are spaced apart from the entire resistor region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the cell gate pattern and the resistor pattern comprise a first metal pattern in contact with underlying layers thereof. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the peripheral circuit gate pattern comprises a first polysilicon pattern in contact with the third insulating layer. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the cell gate pattern and the resistor pattern further comprise at least one pattern comprising a second polysilicon pattern and/or a second metal pattern, the at least one pattern being disposed on the first metal pattern. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the peripheral circuit gate pattern further comprises a conductive pattern on the first polysilicon pattern, the conductive pattern having a same structure as the cell gate pattern and the resistor pattern. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the resistor structure further comprises fourth and fifth insulating layers between the semiconductor substrate and the resistor pattern,
 the fourth and fifth insulating layers comprising same materials as the charge storage layer and the second insulating layer, respectively.   
     
     
         7 . The semiconductor device of  claim 1 , wherein the charge storage layer comprises a nitride layer.