Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns

Abstract

A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

What is claimed is: 
     
         1 . A logic circuit that includes a logic brick that implements a non-standard complex Boolean logic function that has at least three inputs, the logic circuit made by:
 using a computer to determine a circuit that implements the non-standard complex Boolean logic function, the determining including identifying transistors, associated connections and the at least three inputs to implement the circuit, the identifying reducing a number of the transistors to be a fewest possible that satisfy predetermined logic, layout and electrical constraints, and wherein the determining restricts the circuit to a stack depth of no more than 3;   determining a layout for the circuit to specify the logic brick using the computer; and,   using the logic brick layout to implement the logic circuit.   
     
     
         2 . A logic circuit made according to  claim 1 , wherein the determining uses a minimal negative gate algorithm. 
     
     
         3 . A logic circuit that includes a logic brick that implements a non-standard complex Boolean logic function that has at least three inputs, the logic circuit made by:
 determining a circuit that implements the non-standard complex Boolean logic function using the computer, the determining including identifying transistors, associated connections and the at least three inputs to implement the circuit, the identifying reducing a number of the transistors to be a fewest possible that satisfy predetermined logic, layout and electrical constraints, and wherein the determining the circuit uses a recursive decomposition to select an output function for the circuit, and wherein a stack height of the output function is no more than 2;   determining a layout for the circuit to specify the logic brick using the computer; and,   using the logic brick layout to implement the logic circuit.   
     
     
         4 . A logic circuit made according to  claim 3  wherein the determining uses a recursive decomposition and a template matching, wherein the template matching requires that the circuit be substantially obtained from design templates used in the template matching, and wherein each of the design templates is restricted to having a stack depth of no more than 3. 
     
     
         5 . A logic circuit made according to  claim 3  wherein the identifying reduces a number of the transistors to be the fewest possible after the determining (a) uses a minimal gate algorithm, (b) finds a set of Don't Cares that minimizes transistor count, and (3) ensures that the selected transistors are achieved at or below a pre-specified stack height restriction. 
     
     
         6 . A logic circuit made according to  claim 3  wherein one of the predetermined electrical constraints is stack height, one of the predetermined logic constraints is a selected type of logic. 
     
     
         7 . A logic circuit made according to  claim 6  wherein one of the predetermined logic constraints is a logic family that does not include pass transistors. 
     
     
         8 . A logic circuit made according to  claim 6  wherein one of the predetermined layout constraints is using a merged diffusion region for at least some of the transistors. 
     
     
         9 . A logic circuit made according to  claim 3  wherein one of the predetermined layout constraints is using a merged diffusion region for at least some of the transistors. 
     
     
         10 . A logic circuit made according to  claim 9  wherein one of the predetermined logic constraints is a logic family that does not include pass transistors. 
     
     
         11 . A computer-designed, transistor-implemented logic circuit, comprising:
 a plurality of interconnected transistors formed from overlapping polysilicon and diffusion patterns, said interconnected transistors corresponding to a plurality of Transistor Level Bricks (TL bricks), each TL brick corresponding to a set of transistor-based logical gates synthesized from a logical representation of a non-standard complex Boolean logic function;   wherein each TL brick is limited to a stack depth of no more than three.   
     
     
         12 . A logic circuit, as defined in  claim 11 , wherein each TL brick is limited to an output stack height of no more than two.