Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing

Abstract

The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

1 . A microcomputer system, comprising:
 a register file comprising a plurality of registers; and   a load/store unit coupled to the register file and enabled to use a first part of a memory address to load at least a portion of a double-word into a first register of the register file,   wherein a second part of the memory address is used to specify individual bytes within the double-word.   
     
     
         2 . The microcomputer system of  claim 1 , wherein the memory address is formed by adding an index value stored in a second register with a base value stored in a third register. 
     
     
         3 . The microcomputer system of  claim 1 , wherein the load/store unit is enabled to fragment the double-word and load a portion of the double-word in a second register of the register file. 
     
     
         4 . The microcomputer system of  claim 1 , wherein the load/store unit is enabled to use a first part of a memory address to store in memory a double-word from a second register of the register file. 
     
     
         5 . The microcomputer system of  claim 1 , wherein the load/store unit is enabled to concatenate a first double-word and a second double-word and to use a first part of a memory address to store the concatenated double-word in a memory location. 
     
     
         6 . The microcomputer system of  claim 1 , wherein the double-word is unformatted.