Package carrier, semiconductor package, and process for fabricating same

Abstract

A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

1 . A package carrier, comprising:
 a dielectric layer having a plurality of openings;   a first conductive pattern, disposed adjacent to a first surface of the dielectric layer, the first conductive pattern including a plurality of first pads; and   a plurality of conductive vias disposed in respective ones of the openings, wherein each conductive via includes a first via segment, connected to at least one of the first pads, and a second via segment, connected to the first via segment, such that a lateral extent of the first via segment is different from a lateral extent of the second via segment.   
     
     
         2 . The package carrier as claimed in  claim 1 , wherein the first conductive pattern is embedded in the dielectric layer. 
     
     
         3 . The package carrier as claimed in  claim 1 , wherein the lateral extent of the first via segment is greater than the lateral extent of the second via segment. 
     
     
         4 . The package carrier as claimed in  claim 1 , wherein the conductive vias provide a locking mechanism with respect to the dielectric layer. 
     
     
         5 . The package carrier as claimed in  claim 1 , further comprising:
 a second conductive pattern, disposed adjacent to a second surface of the dielectric layer and including a plurality of second pads, wherein the second via segment of each conductive via is connected to at least one of the second pads.   
     
     
         6 . The package carrier as claimed in  claim 5 , further comprising:
 a chip pad support, extending through the dielectric layer,   wherein the first conductive pattern includes a third pad corresponding to a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.   
     
     
         7 . The package carrier as claimed in  claim 6 , wherein the second conductive pattern includes a fourth pad connected to the second support segment, a lateral extent of the first support segment is greater than the lateral extent of the first via segment, and a lateral extent of the second support segment is greater than the lateral extent of the second via segment. 
     
     
         8 . The package carrier as claimed in  claim 7 , wherein the lateral extent of the first support segment is greater than the lateral extent of the second support segment. 
     
     
         9 . The package carrier as claimed in  claim 1 , further comprising:
 a chip pad support, extending through the dielectric layer,   wherein the first conductive pattern includes a chip pad, and the chip pad support includes a first support segment, connected to the chip pad, and a second support segment, connected to the first support segment.   
     
     
         10 . A semiconductor package, comprising:
 a package carrier, including:
 a dielectric layer; 
 a top conductive pattern, disposed adjacent to a top surface of the dielectric layer, and including a plurality of first pads; 
 a bottom conductive pattern, disposed adjacent to a bottom surface of the dielectric layer, and including a plurality of second pads; and 
 a plurality of conductive vias within the dielectric layer and extending between the top conductive pattern and the bottom conductive pattern, wherein each conductive via includes a first segment, connected to at least one of the first pads, and a second segment, connected to at least one of the second pads; and 
   a chip, attached to the package carrier and connected to the first pads.   
     
     
         11 . The semiconductor package as claimed in  claim 10 , wherein the top conductive pattern is embedded in the dielectric layer. 
     
     
         12 . The semiconductor package as claimed in  claim 10 , wherein a lateral extent of the first segment is greater than a lateral extent of the second segment. 
     
     
         13 . The semiconductor package as claimed in  claim 10 , wherein the conductive vias provide a locking mechanism with respect to the dielectric layer. 
     
     
         14 . The semiconductor package as claimed in  claim 10 , wherein a top surface of the top conductive pattern is aligned with the top surface of the dielectric layer. 
     
     
         15 . The semiconductor package as claimed in  claim 10 , wherein the package carrier further includes:
 a chip pad support, extending through the dielectric layer,   wherein the top conductive pattern includes a third pad corresponding to a chip pad, the chip is disposed adjacent to the chip pad, the chip pad support includes a third segment, connected to the chip pad, and a fourth segment, connected to the third segment, the bottom conductive pattern includes a fourth pad connected to the fourth segment, a lateral extent of the third segment is greater than a lateral extent of the first segment, and a lateral extent of the fourth segment is greater than a lateral extent of the second segment.   
     
     
         16 . The semiconductor package as claimed in  claim 15 , further comprising:
 at least one conductive bump, disposed adjacent to the fourth pad.   
     
     
         17 . The semiconductor package as claimed in  claim 10 , wherein the package carrier further includes:
 an etching stop layer, disposed between the conductive vias and the top conductive pattern.   
     
     
         18 . The semiconductor package as claimed in  claim 10 , wherein the conductive vias correspond to conductive posts. 
     
     
         19 . A semiconductor fabrication process, comprising:
 forming a first conductive pattern including a plurality of first pads;   forming a plurality of first via segments on at least some of the first pads;   providing a dielectric layer having a plurality of first openings corresponding to the first via segments;   applying the dielectric layer to the first conductive pattern and the first via segments;   forming a plurality of second openings in the dielectric layer, such that the first via segments are exposed by the second openings; and   forming a plurality of second via segments on the first via segments and at least partially within the second openings, such that a diameter of the first via segment is different than a diameter of the second via segment.   
     
     
         20 . The process as claimed in  claim 19 , further comprising:
 forming a second conductive pattern including a plurality of second pads, wherein the second via segments are connected to at least some of the second pads.