Non-volatile semiconductor memory device

Abstract

A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

1 . A non-volatile semiconductor memory device comprising:
 a select transistor having source and drain regions (termed “source/drain region(s)” hereinafter) on both sides of a channel of a semiconductor substrate and having a gate electrode on the channel via a first gate insulating film;   an element isolation region formed on the semiconductor substrate in an area adjacent to said select transistor;   an antifuse adjacent to said element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode on the semiconductor substrate in an area between said element isolation region and the lower electrode via a second gate insulating film; and   a connection contact electrically connecting one of the source/drain regions and the upper electrode and contacting said one of the source/drain regions and the upper electrode.   
     
     
         2 . The device according to  claim 1 , wherein said connection contact is formed in a single opening that is formed in an interlayer insulating film, which has been formed over said select transistor and said antifuse, and that includes part of the source/drain region and part of the upper electrode as a wall portion of the opening. 
     
     
         3 . The device according to  claim 1 , wherein said connection contact comprises:
 a first connection contact formed in a first opening that is formed in an interlayer insulating film, which has been formed to cover said select transistor and said antifuse, and that includes exposed part of the source/drain regions;   a second connection contact formed in a second opening that is formed in the interlayer insulating film and that includes part of the upper electrode as part of opening wall; and   wiring for electrically connecting said first connection contact and said second connection contact.   
     
     
         4 . The device according to  claim 1 , wherein the first gate insulating film and the second gate insulating film are gate insulating films having a same film thickness. 
     
     
         5 . The device according to  claim 1 , wherein the second gate insulating film is thinner than the first gate insulating film. 
     
     
         6 . The device according to  claim 1 , wherein the lower electrode is a diffusion layer in which impurity of the same conductivity type as that of diffusion layer of the source/drain regions has been introduced. 
     
     
         7 . The device according to  claim 1 , wherein said lower electrode is of an impurity having a conductivity type different from that of the diffusion layer of the source/drain regions. 
     
     
         8 . The device according to  claim 7 , wherein said lower electrode is horizontally not overlapping with said upper electrode as viewed in a direction perpendicular to the substrate. 
     
     
         9 . The device according to  claim 1 , wherein lower electrodes of memory cells, each of which includes said select transistor and said antifuse, are electrically connected to a common source line. 
     
     
         10 . The device according to  claim 1 , wherein said select transistor is of an N-channel-type. 
     
     
         11 . The device according to  claim 1 , wherein said select transistor is of a P-channel-type. 
     
     
         12 . The device according to  claim 1 , further comprising a controller for exercising control in such a manner that when a write operation is performed, the semiconductor substrate and lower electrode are placed at a positive potential and the drain region and gate electrode are placed at ground potential. 
     
     
         13 . The device according to  claim 1 , further comprising a controller for exercising control in such a manner that when a read operation is performed, the semiconductor substrate and lower electrode are placed at ground potential and the drain region and gate electrode are placed at a positive potential. 
     
     
         14 . The device according to  claim 1 , wherein said select transistor is of an N-channel-type and is constructed on a P-well that has been formed in the semiconductor substrate; and
 said antifuse is of a P-channel-type and is constructed on an N-well that has been formed in the semiconductor substrate.   
     
     
         15 . The device according to  claim 14 , further comprising a controller for exercising control in such a manner that when a write operation is performed, the P-well of said select transistor and the N-well of said antifuse are placed at ground potential, the lower electrode of said antifuse is placed at a negative potential and the drain region and gate electrode of said select transistor are placed at a positive potential. 
     
     
         16 . The device according to  claim 1 , wherein said select transistor is of a P-channel-type and is constructed on an N-well that has been formed in said semiconductor substrate; and
 said antifuse is of an N-channel-type and is constructed on a P-well that has been formed in said semiconductor substrate.   
     
     
         17 . The device according to  claim 16 , further comprising a controller for exercising control in such a manner that when a write operation is performed, the P-well of said antifuse and the lower electrode are placed at ground potential, the N-well and drain region of said select transistor are placed at a positive potential and the gate electrode is placed at ground potential. 
     
     
         18 . The device according to  claim 1 , further comprising a capacitor at an upper portion of said antifuse, said capacitor having a capacitor lower electrode, a capacitor insulating film and a capacitor upper electrode stacked from bottom to top in the order mentioned;
 wherein the capacitor lower electrode is electrically connected to said connection contact.   
     
     
         19 . The device according to  claim 18 , wherein lower electrodes of memory cells, each of which includes said select transistor, said antifuse and said capacitor, are electrically connected to a common plate line. 
     
     
         20 . The device according to  claim 18 , further comprising a controller for exercising control in such a manner that when a write operation is performed, the semiconductor substrate and lower electrode are placed at ground potential and a positive potential higher than the potential applied to the drain region is applied to the gate electrode, after which potentials of the drain region and gate electrode are lowered and a positive potential is applied to the capacitor upper electrode.