Chip package and fabrication method thereof

Abstract

A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

1 . A chip package, comprising:
 a semiconductor substrate, having a device area and a peripheral bonding pad area, wherein the peripheral bonding pad area surrounds the device area;   a plurality of conductive pads disposed at the peripheral bonding pad area of the semiconductor substrate;   a chip passivation layer disposed over the semiconductor substrate and exposing the conductive pads;   an insulating protective layer disposed over the device area; and   a packaging layer disposed on the insulating protective layer and exposing the conductive pads.   
     
     
         2 . The chip package as claimed in  claim 1 , wherein the insulating protective layer covers the device area, not reaching to the peripheral bonding pad area, and the conductive pads and the chip passivation layer at the peripheral bonding pad area are exposed by the packaging layer. 
     
     
         3 . The chip package as claimed in  claim 1 , further comprising a spacer disposed between the packaging layer and the insulating protective layer. 
     
     
         4 . The chip package as claimed in  claim 1 , further comprising a cavity formed between the packaging layer and the insulating protective layer, wherein the cavity is surrounded by the spacer. 
     
     
         5 . The chip device package as claimed in  claim 1 , wherein the material of the insulating protective layer is different from the material of the chip passivation layer. 
     
     
         6 . The chip device package as claimed in  claim 5 , wherein the material of the chip passivation layer comprises silicon nitride and the material of the insulating protective layer comprises silicon oxide. 
     
     
         7 . The chip package as claimed in  claim 5 , wherein the material of the insulating protective layer comprises a photosensitive insulating material. 
     
     
         8 . The chip package as claimed in  claim 4 , wherein a portion of the insulating protective layer under the spacer has hardness which is greater than that of other portions of the insulating protective layer. 
     
     
         9 . The chip package as claimed in  claim 5 , wherein the packaging layer comprises a transparent substrate or a semiconductor substrate. 
     
     
         10 . A method for fabricating a chip package, comprising:
 providing a semiconductor wafer, containing a plurality of device areas and a peripheral bonding pad area disposed between any two adjacent device areas, wherein the peripheral bonding pad area includes a plurality of conductive pads, and a chip passivation layer covering the semiconductor wafer and exposing the conductive pads;   forming an insulating protective layer on the chip passivation layer, covering the conductive pads;   providing a packaging layer;   bonding the semiconductor wafer with the packaging layer;   patterning the packaging layer to form a plurality of openings, exposing the insulating protective layer at the peripheral bonding pad area; and   using the packaging layer as a hard mask to remove the insulating protective layer at the peripheral bonding pad area, exposing the conductive pads.   
     
     
         11 . The method as claimed in  claim 10 , wherein the step of patterning the packaging layer comprises a cutting process and wherein during the cutting process, the conductive pads are covered with the insulating protective layer. 
     
     
         12 . The method as claimed in  claim 11 , wherein the step of removing the insulating protective layer comprises an etching process. 
     
     
         13 . The method as claimed in  claim 10 , wherein the material of the insulating protective layer is different from the material of the chip passivation layer. 
     
     
         14 . The method as claimed in  claim 13 , wherein the material of the chip passivation layer comprises silicon nitride and the material of the insulating protective layer comprises silicon oxide. 
     
     
         15 . The method as claimed in  claim 10 , wherein the material of the insulating protective layer comprises a photosensitive insulating material. 
     
     
         16 . The method as claimed in  claim 10 , further comprising;
 forming a spacer between the packaging layer and the insulating protective layer; and   forming a cavity between the packaging layer and the insulating protective layer, wherein the cavity is surrounded by the spacer.   
     
     
         17 . The method as claimed in  claim 16 , further comprising performing an exposure process to the photosensitive insulating material, wherein a portion of the photosensitive insulating material disposed under the spacer are exposed to an exposure extent smaller than that of other portions of the photosensitive insulating material. 
     
     
         18 . The method as claimed in  claim 17 , wherein the portion of the insulating protective layer disposed under the spacer has hardness which is greater than that of the other portions of the insulating protective layer. 
     
     
         19 . The method as claimed in  claim 16 , wherein the packaging layer comprises a transparent substrate or a semiconductor substrate.