Semiconductor device having sufficient process margin and method of forming same

Abstract

According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

1 - 12 . (canceled) 
     
     
         13 . A method of manufacturing a semiconductor device comprising:
 first forming at least three active patterns and P type and N type impurity regions in a substrate, the at least three active patterns being positioned in the P type and N type impurity regions and being parallel to one another and arranged in a first direction, the at least three active patterns having a first pitch between adjacent ones of the at least three active patterns in the first direction and extending longitudinally in a second direction, the second direction being perpendicular to the first direction; and   second forming at least three gate patterns, each of the at least three gate patterns on at least one of the at least three active patterns, the at least three gate patterns being parallel to one another and arranged in the second direction, each of the at least three gate patterns extending longitudinally in the first direction, the at least three gate patterns having a uniform second pitch between adjacent ones of the at least three gate patterns in the second direction.   
     
     
         14 . The method of  claim 13 , wherein the at least three active patterns have a uniform first pitch between adjacent ones of the at least three active patterns in the first direction. 
     
     
         15 . The method of  claim 13 , further comprising:
 forming contact holes, at least one of contact holes being on one of the at least three active patterns and between two of the at least three gate patterns, the contact holes having a uniform pitch between adjacent ones of the at least one contact holes in the second direction.   
     
     
         16 . The method of  claim 14 , wherein the first pitch is substantially the same as the second pitch. 
     
     
         17 . A method of manufacturing a logic device comprising:
 first forming at least three active patterns and P type and N type impurity regions in a substrate, the at least three active patterns being positioned in the P type and N type impurity regions and being parallel to one another and arranged in a first direction, the at least three active patterns having pitches between adjacent ones of the at least three active patterns in the first direction and extending longitudinally in a second direction, the second direction being perpendicular to the first direction; and   second forming at least three gate patterns, each of the at least three gate patterns on at least one of the at least three active patterns, the at least three gate patterns being parallel to one another and arranged in the second direction, each of the at least three gate patterns extending longitudinally in the first direction, the at least three gate patterns having a uniform pitch between adjacent ones of the at least three gate patterns in the second direction.   
     
     
         18 . The method of  claim 17 , wherein the at least three active patterns have a uniform pitch between adjacent ones of the at least three active patterns. 
     
     
         19 . The method of  claim 17 , further comprising:
 forming contact holes, at least one contact hole being on the at least three active patterns and between two of the at least three gate patterns, the contact holes having a uniform pitch between adjacent ones of the at least one contact holes in the first second direction.   
     
     
         20 . The method of  claim 18 , wherein the uniform pitch between adjacent ones of the at least three active patterns is substantially the same as the uniform pitch between adjacent ones of the at least three gate patterns. 
     
     
         21 . The method of  claim 18 , wherein the P type impurity region and the N type impurity region are positioned in a unit cell region, the unit cell region has a first side and a second side substantially perpendicular to the first side, the first side of the unit cell region has a length substantially equal to an integral multiple of the first pitch. 
     
     
         22 . The method of  claim 19 , wherein the P type impurity region and the N type impurity region are positioned in a unit cell region, the unit cell region has a first side and a second side substantially perpendicular to the first side, the first side of the unit cell region has a length substantially equal to an integral multiple of the first pitch. 
     
     
         23 . The method of  claim 19 , further comprising:
 forming an insulating interlayer on the active and gate patterns;   etching the insulating interlayer to form contact holes partially exposing surfaces of the active and gate patterns, the contact holes being disposed to have third pitches in an X direction and fourth pitches in a Y direction substantially perpendicular to the X direction, the third pitches being substantially equal to an integral multiple of a minimum pitch among the third pitches, and the fourth pitches being substantially equal to an integral multiple of a minimum pitch among the fourth pitches; and   filling the contact holes with a conductive layer to form contacts.   
     
     
         24 . The method of  claim 23 , wherein forming the contact holes comprises:
 forming a photoresist layer on the insulating interlayer;   exposing the photoresist layer using an exposure mask to form a photoresist pattern; and   etching the insulating interlayer using the photoresist pattern as an etching mask.   
     
     
         25 . The method of  claim 24 , wherein the exposure mask comprises contact patterns for forming the contacts and dummy contact patterns disposed between the contact patterns. 
     
     
         26 . The method of  claim 25 , wherein the contact patterns and the dummy contact patterns are uniformly spaced apart from each other. 
     
     
         27 . A semiconductor device comprising:
 P type and N type impurity regions of a substrate;   at least three active patterns in the P type and N type impurity regions, the at least three active patterns being parallel to one another and arranged in a first direction, the at least three active patterns having pitches between adjacent ones of the at least three active patterns in the first direction and extending longitudinally in a second direction, the second direction being perpendicular to the first direction; and   at least three gate patterns, each of the at least three gate patterns on at least one of the at least three active patterns, the at least three gate patterns being parallel to one another and arranged in the second direction, each of the at least three gate patterns extending longitudinally in the first direction, the at least three gate patterns having a uniform pitch between adjacent ones of the at least three gate patterns in the second direction.   
     
     
         28 . The semiconductor device of  claim 27 , wherein the at least three active patterns have a uniform pitch between adjacent ones of the at least three active patterns. 
     
     
         29 . The semiconductor device of  claim 27 , further comprising:
 forming contact holes, at least one contact hole being on the at least three active patterns and between two of the at least three gate patterns, the contact holes having a uniform pitch between adjacent ones of the at least one contact holes in the second direction.   
     
     
         30 . The semiconductor device of  claim 28 , wherein the uniform pitch between adjacent ones of the at least three active patterns is substantially the same as the uniform pitch between adjacent ones of the at least three gate patterns. 
     
     
         31 . A logic device comprising:
 P type and N type impurity regions of a substrate;   at least three active patterns in the P type and N type impurity regions, the at least three active patterns being parallel to one another and arranged in a first direction, the at least three active patterns having pitches between adjacent ones of the at least three active patterns in the first direction and extending longitudinally in a second direction, the second direction being perpendicular to the first direction; and   at least three gate patterns, each of the at least three gate patterns on at least one of the at least three active patterns, the at least three gate patterns being parallel to one another and arranged in the second direction, each of the at least three gate patterns extending longitudinally in the first direction, the at least three gate patterns having a uniform pitch between adjacent ones of the at least three gate patterns in the second direction.   
     
     
         32 . The logic device of  claim 31 , wherein the at least three active patterns have a uniform pitch between adjacent ones of the at least three active patterns. 
     
     
         33 . The logic device of  claim 31 , further comprising:
 forming contact holes, at least one contact hole being on the at least three active patterns and between two of the at least three gate patterns, the contact holes having a uniform pitch between adjacent ones of the at least one contact holes in the second direction.   
     
     
         34 . The logic device of  claim 32 , wherein the uniform pitch between adjacent ones of the at least three active patterns is substantially the same as the uniform pitch between adjacent ones of the at least three gate patterns. 
     
     
         35 . The logic device of  claim 32 , wherein a P type impurity region and the N type impurity region are positioned in a unit cell region, the unit cell region has a first side and a second side substantially perpendicular to the first side, the first side of the unit cell region has a length substantially equal to an integral multiple of the first pitch. 
     
     
         36 . The logic device of  claim 33 , wherein the P type impurity region and the N type impurity region are positioned in a unit cell region, the unit cell region has a first side and a second side substantially perpendicular to the first side, the first side of the unit cell region has a length substantially equal to an integral multiple of the first pitch.