Method for memory cell characterization using universal structure

Abstract

A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell.

1 . A test method comprising:
 providing an integrated circuit, wherein said integrated circuit comprises a first memory base cell, wherein said first memory base cell comprises a first storage node set, a set of other nodes, and a plurality of circuit elements each having a plurality of terminals, wherein said first storage node set is the only storage node set in said first memory base cell, wherein said set of other nodes comprises a first data node for accessing said first storage node set, a first access control node for controlling the access of said first storage node set, and a reference node for said first storage node set; and   conducting a circuit element test on each circuit element in said set of circuit elements, wherein in each of said circuit element test on each circuit element each terminal of said each circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of said each circuit element.   
     
     
         2 . The test method of  claim 1 , further comprising a full cell test in which each node in said set of other nodes is forced with a voltage, all nodes in said first storage node set are connected together without being forced with an electrical quantity, and an electrical quantity is directly measured from said first data node. 
     
     
         3 . The test method of  claim 1 , wherein said integrated circuit further comprises a plurality of other memory base cells, wherein said first memory base cell and said plurality of other memory base cells together form an array having substantially the same configuration as a memory array, wherein each of said other memory base cells is substantially the same as said first memory base cell, wherein each of said other memory base cells is adjacent to said first memory base cell, and wherein at least one of the access control nodes in said other memory base cells and nodes in the storage node sets in said other memory base cells is forced with a voltage to cut off sneak path during a test. 
     
     
         4 . An integrated circuit comprising a memory cell formed based on data collected from a characterization using the test method of  claim 1 . 
     
     
         5 . The test method of  claim 1 , wherein said integrated circuit comprises a first structure comprising said first memory base cell, a first port set, and a set of other ports, wherein each node in said first storage node set is connected to a port in said first port set, wherein each of said other nodes is connected to one of said other ports, and wherein each of said other ports is connected to one and only one of said other nodes. 
     
     
         6 . The integrated circuit of  claim 5 , wherein said set of other nodes further comprises a second data node for accessing said first storage node set and a second access control node for controlling the access of said first storage node set. 
     
     
         7 . The integrated circuit of  claim 5 , wherein said plurality of circuit elements comprises a transistor having a body terminal, and wherein said set of other nodes further comprises a body node connected to said body terminal. 
     
     
         8 . The integrated circuit of  claim 5 , further comprising a plurality of other structures each being selected from the group consisting of a probe pad, a bond pad, and a bump, wherein each port in said first port set and said set of other ports is connected to one of said other structures, and wherein each of said other structures is connected to one and only one port in said first port set and said set of other ports. 
     
     
         9 . The integrated circuit of  claim 5 , wherein said first structure further comprises a plurality of other memory base cells and a third port set, wherein said first memory base cell and said plurality of other memory base cells together form an array having substantially the same configuration as a memory array, wherein each of said other memory base cells is substantially the same as said first memory base cell, wherein each of said other memory base cells is adjacent to said first memory base cell, and wherein at least one of the access control nodes in said other memory base cells and nodes in the storage node sets in said other memory base cells is connected to a port in said third port set. 
     
     
         10 . The integrated circuit of  claim 5 , wherein at least two nodes in said first storage node set are connected to a same port in said first port set. 
     
     
         11 . The integrated circuit of  claim 5 , wherein said first port set consists of one and only one port. 
     
     
         12 . The test method of  claim 1 , wherein said integrated circuit further comprising:
 a first structure comprising said first memory base cell, a first port set, and a set of other ports, wherein each node in said first storage node set is connected to a port in said first port set, wherein each of said other nodes is connected to one of said other ports, and wherein each of said other ports is connected to one and only one of said other nodes; and   a memory cell comprising a storage node and a second memory base cell, wherein said storage node is the only storage node in said memory cell, wherein said second memory base cell is substantially the same as said first memory base cell, wherein said second memory base cell comprises a second storage node set substantially the same as said first storage node set, and wherein said storage node comprises said second storage node set.   
     
     
         13 . The integrated circuit of  claim 12 , wherein said set of other nodes further comprises a second data node for accessing said first storage node set and a second access control node for controlling the access of said first storage node set. 
     
     
         14 . The integrated circuit of  claim 12 , wherein said plurality of circuit elements comprises a transistor having a body terminal, and wherein said set of other nodes further comprises a body node connected to said body terminal. 
     
     
         15 . The integrated circuit of  claim 12 , further comprising a plurality of other structures each being selected from the group consisting of a probe pad, a bond pad, and a bump, wherein each port in said first port set and said set of other ports is connected to one of said other structures, and wherein each of said other structures is connected to one and only one port in said first port set and said set of other ports. 
     
     
         16 . The integrated circuit of  claim 12 , wherein said first structure further comprises a plurality of other memory base cells and a third port set, wherein said first memory base cell and said plurality of other memory base cells together form an array having substantially the same configuration as a memory array, wherein each of said other memory base cells is substantially the same as said first memory base cell, wherein each of said other memory base cells is adjacent to said first memory base cell, and wherein at least one of the access control nodes in said other memory base cells and nodes in the storage node sets in said other memory base cells is connected to a port in said third port set. 
     
     
         17 . The integrated circuit of  claim 12 , wherein at least two nodes in said first storage node set are connected to a same port in said first port set. 
     
     
         18 . The integrated circuit of  claim 12 , wherein said first port set consists of one and only one port. 
     
     
         19 . The integrated circuit of  claim 12 , wherein said first structure further comprises a third memory base cell substantially the same as said first memory base cell, wherein each node in said first storage node set and said set of other nodes is connected to the corresponding node in said third memory base cell. 
     
     
         20 . The integrated circuit of  claim 12 , further comprising a second structure selected from the group consisting of on-chip parametric measurement structures and multiplexed structures, wherein said second structure comprises said first structure. 
     
     
         21 . The integrated circuit of  claim 12 , wherein said first memory base cell is substantially the same as said memory cell up through a layer selected from the group consisting of a gate layer, a contact layer, and a metal1 layer. 
     
     
         22 . The integrated circuit of  claim 12 , wherein said first structure is in scribe line.