Methods for forming self-aligned dual stress liners for cmos semiconductor devices

Abstract

CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

1 . A dual stress liner (DSL) complementary metal oxide semiconductor (CMOS) device, comprising:
 a semiconductor substrate comprising first and second device regions formed on an active surface of the semiconductor substrate and separated by an isolation region, the first and second device regions including respective first type and second type transistor devices having polyconductor gate electrode and the isolation region comprising a polyconductor line formed thereon;   a self aligned DSL structure comprising a first stress liner layer conformally covering the first type transistor devices in the first device region and a portion of the polyconductor line in the isolation region and a second stress liner layer conformally covering the second type transistor devices in the second device region and a portion of the polyconductor line in the isolation region,   a first layer of insulating material disposed in gaps between adjacent polyconductor gate electrodes in the first device region and in gaps between polyconductor gate electrodes in the first device region and the polyconductor line in the isolation region;   a second layer of insulating material disposed in gaps between adjacent polyconductor gate electrodes in the second device region and in gaps between polyconductor gate electrodes in the second device region and the polyconductor line in the isolation region;   a third layer of insulating material formed over the substrate surface covering the first and second insulating materials in the gaps and covering the portions of the first and second stress liner layers atop the polyconductor gate electrodes in the first and second device regions and the polyconductor line in the isolation region between polyconductor gate electrodes and polyconductor line.   
     
     
         2 . The device of  claim 1 , wherein the first and second stress liner layers are formed having substantially the same thickness. 
     
     
         3 . The device of  claim 1 , wherein the first and second stress liner layers are formed of silicon nitride and wherein the first, second and third layers of insulating material are formed of silicon oxide. 
     
     
         4 . The device of  claim 3 , wherein the first and second insulating layers are formed of a thermal CVD silicon oxide, and wherein the third insulating layer is formed of a plasma CVD silicon oxide. 
     
     
         5 . The device of  claim 3 , wherein the first stress liner layer is formed of a tensile stressed silicon nitride layer, and wherein the first layer of insulating material is formed of a tensile stressed silicon oxide. 
     
     
         6 . The device of  claim 3 , wherein the second stress liner layer is formed of a compressive stressed silicon nitride layer and wherein the second layer of insulating material is formed of a compressive stressed silicon oxide. 
     
     
         7 . The device of  claim 3 , wherein the third layer of insulating layer is formed of a compressive or tensile stressed plasma CVD silicon oxide.