Nonvolatile memory device and method of fabricating the same

Abstract

A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

1 - 30 . (canceled) 
     
     
         31 . A nonvolatile memory device, comprising:
 a tunnel dielectric layer, a charge trap layer, a blocking insulating layer and a first conductive layer sequentially stacked on a semiconductor substrate;   isolation layers protruding as high as a height of the first conductive layer in isolation regions of the semiconductor substrate and configured to isolate the tunnel dielectric layer, the charge trap layer, the blocking insulating layer and the first conductive layer from a neighboring tunnel dielectric layer, a neighboring charge trap layer, a neighboring blocking insulating layer and a neighboring first conductive layer; and   a second conductive layer and a metal gate layer sequentially stacked on the isolation layers and the first conductive layer.   
     
     
         32 . The nonvolatile memory device of  claim 31 , further comprising:
 an insulating layer for a transistor formed in a peripheral region of the semiconductor substrate;   an isolation layer protruding as high as a height of the insulating layer for the transistor in the peripheral region of the semiconductor substrate and configured to isolate the insulating layer for the transistor from neighboring insulating layers for a transistor; and   the first conductive layer and the second conductive layer sequentially stacked on the isolation layer and the insulating layer for the transistor, of the peripheral region.   
     
     
         33 . The nonvolatile memory device of  claim 31 , wherein the charge trap layer is formed of a nitride layer or a mixed layer of an oxide layer and a nitride layer. 
     
     
         34 . The nonvolatile memory device of  claim 31 , wherein the charge trap layer is formed of HFO 2 , ZrO 2 , HFAlO, HFSiO, ZrAlO or ZrSiO. 
     
     
         35 . The nonvolatile memory device of  claim 31 , wherein the charge trap layer is formed to a thickness of 40 to 200 angstroms. 
     
     
         36 . The nonvolatile memory device of  claim 31 , wherein the blocking insulating layer is formed of hafnium oxide, aluminum oxide or zirconium oxide. 
     
     
         37 . The nonvolatile memory device of  claim 31 , wherein the first conductive layer is formed of a polysilicon layer or a metal layer. 
     
     
         38 . The nonvolatile memory device of  claim 38 , wherein the polysilicon layer is formed of a polysilicon layer doped with a N+ impurity. 
     
     
         39 . The nonvolatile memory device of  claim 38 , wherein the metal layer is formed of TaN layer. 
     
     
         40 . The nonvolatile memory device of  claim 32 , wherein the insulating layer for the transistor is formed to a thickness of 500 to 600 angstroms in the case of a high voltage transistor, and the insulating layer for the transistor is formed to a thickness of 200 to 500 angstroms in the case of a low voltage transistor.