Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods

Abstract

A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

1 . A semiconductor device, comprising:
 a substrate having a layer of semiconductor material;   a gate structure overlying the layer of semiconductor material;   source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses;   source/drain implant regions formed in the remaining semiconductor material; and   epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 source/drain extension implants formed in the layer of semiconductor material located below the gate structure; and   tilted halo implants formed in the layer of semiconductor material located below the gate structure.   
     
     
         3 . The semiconductor device of  claim 1 , wherein:
 the substrate is a silicon-on-insulator (SOI) substrate having a layer of insulator material;   the layer of semiconductor material is disposed on the layer of insulator material; and   the source/drain implant regions are butted against the layer of insulator material.   
     
     
         4 . The semiconductor device of  claim 1 , wherein:
 the semiconductor device is an NMOS transistor device;   the source/drain implant regions are N-type regions; and   the semiconductor material in the source/drain recesses is N-type semiconductor material.   
     
     
         5 . The semiconductor device of  claim 1 , wherein:
 the semiconductor device is a PMOS transistor device;   the source/drain implant regions are P-type regions; and   the semiconductor material in the source/drain recesses is P-type semiconductor material.   
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 metal silicide contact areas formed on the in situ doped semiconductor material;   an insulating layer formed over the gate structure, over the in situ doped semiconductor material, and over the metal silicide contact areas; and   conductive plugs formed in the insulating layer, the conductive plugs contacting the metal silicide contact areas.   
     
     
         7 . A semiconductor device, comprising:
 a silicon-on-insulator (SOI) substrate having a layer of insulator material and a layer of semiconductor material on the layer of insulator material;   a gate structure overlying the layer of semiconductor material;   source/drain recesses in the layer of semiconductor material adjacent to the gate structure, wherein the source/drain recesses are at least partially filled with in situ doped semiconductor material;   remaining semiconductor material below the source/drain recesses; and   butted source/drain implant regions in the remaining semiconductor material that extend to and are butted against the layer of insulator material.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the in situ doped semiconductor material comprises epitaxially grown, in situ doped semiconductor material. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the semiconductor device is an NMOS transistor device, wherein the butted source/drain implant regions comprise butted N-type source/drain implant regions, and wherein the in situ doped semiconductor material in the source/drain recesses comprises N-type in situ doped semiconductor material. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the semiconductor device is a PMOS transistor device, wherein the butted source/drain implant regions comprise butted P-type source/drain implant regions, and wherein the in situ doped semiconductor material in the source/drain recesses comprises P-type in situ doped semiconductor material. 
     
     
         11 . The semiconductor device of  claim 7 , further comprising:
 metal silicide contact areas on the in situ doped semiconductor material.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising:
 an insulating layer overlying the gate structure, the in situ doped semiconductor material, and the metal silicide contact areas; and   conductive plugs in the insulating layer, the conductive plugs contacting the metal silicide contact areas.   
     
     
         13 . The semiconductor device of  claim 7 , wherein the gate structure overlying the layer of semiconductor material has a height of less than  70  nanometers, and wherein the butted source/drain implant regions have a depth that is less than the height of the gate structure. 
     
     
         14 . The semiconductor device of  claim 7 , further comprising:
 source/drain extension implants formed in the layer of semiconductor material located below the gate structure; and   tilted halo implants formed in the layer of semiconductor material located below the gate structure.   
     
     
         15 . A semiconductor device, comprising:
 a silicon-on-insulator (SOI) substrate comprising a buried oxide layer and a layer of silicon material on the buried oxide layer;   a device structure on the SOI substrate, the device structure comprising: a gate structure overlying the layer of silicon material, and source/drain extension implant regions in the layer of silicon material;   source/drain recesses in the layer of silicon material adjacent to the gate structure, wherein the source/drain recesses are at least partially filled with epitaxially-grown, in situ doped semiconductor material;   remaining silicon material below the source/drain recesses; and   butted source/drain implant regions in the remaining silicon material that extend to the buried oxide layer.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the butted source/drain implant regions comprise ions of an impurity that are implanted into the remaining silicon material. 
     
     
         17 . The semiconductor device of  claim 15 , further comprising:
 metal silicide contact areas on the in situ doped semiconductor material.   
     
     
         18 . The semiconductor device of  claim 17 , further comprising:
 source/drain extension implants formed in the layer of silicon material located below the gate structure; and   tilted halo implants formed in the layer of silicon material located below the gate structure.   
     
     
         19 . The semiconductor device of  claim 17 , wherein the gate structure has a height of less than 70 nanometers, and wherein the butted source/drain implant regions have a depth that is less than the height of the gate structure. 
     
     
         20 . The semiconductor device of  claim 15 , wherein the semiconductor device is either an NMOS transistor device or a PMOS transistor device,
 wherein the butted source/drain implant regions comprise butted N-type source/drain implant regions, and the in situ doped semiconductor material in the source/drain recesses comprises N-type in situ doped semiconductor material when the semiconductor device is the NMOS transistor device, and   wherein the butted source/drain implant regions comprise butted P-type source/drain implant regions, and the in situ doped semiconductor material in the source/drain recesses comprises P-type in situ doped semiconductor material when the semiconductor device is a PMOS transistor device.