Semiconductor Memory Device Having Three Dimensional Structure

Abstract

A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

1 . A. semiconductor device, comprising:
 a semiconductor substrate having a cell region and a peripheral circuit region;   bulk transistors arranged on the semiconductor substrate of the cell region;   an interlayer insulator pattern arranged in the cell region to cover the bulk transistors;   thin film transistors arranged on the interlayer insulator pattern;   a peripheral body pattern arranged to contact the semiconductor substrate of the peripheral circuit region; and   peripheral transistors arranged in the peripheral body pattern, the peripheral transistors arranged to be located on the substantially same imaginary horizontal line as the thin film transistors of the cell region.