Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type
Abstract
The invention concerns a process to treat a structure of semiconductor-on-insulator type structure of a carrier substrate, an oxide layer and a thin layer of a semiconductor material, wherein the structure having a peripheral ring in which the oxide layer is exposed, and the process includes the application of a main thermal treatment in a neutral or controlled reducing atmosphere. The method includes a step to cover at least an exposed peripheral part of the oxide layer, prior to the main thermal treatment, this latter treatment being conducted under controlled time and temperature conditions so as to urge at least part of the oxygen in the oxide layer to diffuse through the thin semiconductor layer, leading to controlled reduction of the thickness of the oxide layer.
Claims
exact text as granted — not AI-modified1 .- 12 . (canceled)
13 . A process for treating a semiconductor-on-insulator structure, with the substrate successively comprising a carrier substrate, an oxide layer, a thin layer of semiconductor material, and a peripheral ring in which the oxide layer is exposed, which process comprises covering at least an exposed peripheral part of the oxide layer prior to applying a main thermal treatment, conducting the main thermal treatment in a neutral or controlled reducing atmosphere under controlled time and temperature conditions to cause some oxygen of the oxide layer to diffuse through the thin semiconductor layer rather than into the atmosphere, leading to controlled reduction of the thickness of the oxide layer in a beneficial manner.
14 . The process according to claim 13 , wherein the main thermal treatment is a smoothing thermal treatment which smoothes the thin layer.
15 . The process according to claim 13 , which further comprises applying an additional creep thermal treatment directly before the main thermal treatment to cause creep of the semiconductor layer over the exposed peripheral part of the oxide layer.
16 . The process according to claim 15 , wherein the creep thermal treatment is conducted by very rapid application of a thermal treatment at a final temperature in the order of 1200° C.
17 . The process according to claim 16 , wherein the creep thermal treatment is performed with a temperature rise of more than 20° C./second.
18 . The process according to claim 16 , wherein the creep thermal treatment is performed with a temperature rise of more than 50° C./second.
19 . The process according to claim 15 , wherein the creep thermal treatment is conducted at the final temperature for a time of less than 3 minutes.
20 . The process according to claim 15 , wherein the creep thermal treatment is conducted in an atmosphere of hydrogen and/or argon.
21 . The process according to claim 13 , wherein the oxide layer has a thickness in the order of 10 nm, while the thin layer has a thickness at least ten times greater.
22 . The process according to claim 13 , wherein, prior to conducting the main thermal treatment the covering includes forming a mask on the exposed peripheral part of the buried oxide.
23 . The process according to claim 22 , wherein the mask is formed locally on the semiconductor layer to allow local dissolution during the main thermal treatment.
24 . The process according to claim 15 , wherein, prior to conducting the main thermal treatment but after the creep thermal treatment the covering includes forming a mask on the exposed peripheral part of the buried oxide.
25 . The process according to claim 24 , wherein the mask is formed locally on the semiconductor layer to allow local dissolution during the main thermal treatment.
26 . The process according to claim 13 , wherein the layer of semiconductor material comprises silicon.
27 . The process according to claim 26 , wherein the oxide layer comprises silicon oxide.
28 . The process according to claim 13 , wherein the oxide layer comprises silicon oxide.Join the waitlist — get patent alerts
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