Memory Device Using A Dual Layer Conductive Metal Oxide Structure

Abstract

Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO x , LaSrCoO x , LaNiO x , etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the un-etched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

1 . A re-writeable non-volatile memory device, comprising:
 a re-writeable non-volatile two-terminal memory element (ME) including electrically in series with a first electrode and a second electrode,
 a dual-layer conductive metal oxide (CMO) structure including only a first CMO having a first thickness and a second CMO having a second thickness that is less than the first thickness, the first CMO in direct contact with the first electrode and the second CMO is in direct contact with the first CMO, the first CMO and the second CMO are positioned between and are substantially aligned with the first and second electrodes, and 
 an electronically insulating material having a third thickness, the layer of electronically insulating material is in direct contact with the second CMO and the second electrode. 
   
     
     
         2 . The memory device of  claim 1 , wherein the third thickness is approximately 35 Angstroms or less. 
     
     
         3 . The memory device of  claim 1 , wherein the first CMO and the second CMO are made from different CMO materials. 
     
     
         4 . The memory device of  claim 1 , wherein the first CMO and the second CMO are made from different CMO materials selected from the group consisting of PrCaMnO x  (PCMO), LaNiO x  (LNO), SrRuO x  (SRO), LaSrCrO x  (LSCrO), LaCaMnO x  (LCMO), LaSrCaMnO x  (LSCMO), LaSrMnO x  (LSMO), LaSrCoO x  (LSCoO), and LaSrFeO x  (LSFeO). 
     
     
         5 . The memory device of  claim 1 , wherein the first CMO comprises a material selected from the group consisting of PrCaMnO x , LaNiO 3 , and LaCoO 3 . 
     
     
         6 . The memory device of  claim 1 , wherein the first CMO has a first stoichiometry and the second CMO has a second stoichiometry, and the second stoichiometry is different than the first stoichiometry. 
     
     
         7 . The memory device of  claim 6 , wherein the first CMO and the second CMO are made from a substantially identical CMO material. 
     
     
         8 . The memory device of  claim 1 , wherein the first CMO, the second CMO or both are made from a conductive binary oxide material. 
     
     
         9 . The memory device of  claim 1 , wherein the first CMO, the second CMO or both include mobile oxygen ions. 
     
     
         10 . The memory device of  claim 9 , wherein at least a portion of the mobile oxygen ions are transported into or out of the electronically insulating material when a write voltage is applied across the first and second electrodes. 
     
     
         11 . The memory device of  claim 1 , wherein the second thickness is less than the first thickness by approximately a factor of 2 or more. 
     
     
         12 . The memory device of  claim 1 , wherein the third thickness is configured for electron tunneling when a voltage for a data operation is applied across the first and second electrodes. 
     
     
         13 . The memory device of  claim 1 , wherein the first thickness is in a range from about 35 Angstroms to about 250 Angstroms. 
     
     
         14 . The memory device of  claim 1 , wherein the second thickness is in a range from about 5 Angstroms to about 50 Angstroms. 
     
     
         15 . The memory device of  claim 1 , wherein the second CMO comprises a material selected from the group consisting of LaSrCoO x , LaNiO 3 , La 2 NiO 4 , La 2 CoO 4 . 
     
     
         16 . The memory device of  claim 1 , wherein the first CMO has a first crystalline structure and the second CMO has a second crystalline structure that is an exact or nearly exact replica of the first crystalline structure. 
     
     
         17 . The memory device of  claim 1 , wherein the first CMO is in contact with and is partially surrounded by a first electrically non-conductive insulating metal oxide (first IMO) and the second CMO is in contact with and is partially surrounded by a second electrically non-conductive insulating metal oxide (second IMO). 
     
     
         18 . The memory device of  claim 17 , wherein the first IMO and the second IMO comprise ion implanted regions of continuous and un-etched layers of the first CMO and the second CMO respectively. 
     
     
         19 . The memory device of  claim 1 , wherein the electronically insulating material comprises a continuous and un-etched layer having portions that are not positioned between the first and second electrodes of the ME. 
     
     
         20 . The memory device of  claim 1 , wherein the ME retains stored data in the absence of electrical power. 
     
     
         21 . The memory device of  claim 1  and further comprising:
 a plurality of the re-writeable non-volatile two-terminal memory elements (ME's) configured in a cross-point array where each ME is positioned between a unique pair of a plurality of conductive array lines of a two-terminal cross-point array and the first and second electrodes of the ME are directly electrically coupled with and electrically in series with its respective unique pair of conductive array lines. 
 
     
     
         22 . The memory device of  claim 21  and further comprising:
 a semiconductor substrate having a front-end-of-the-line (FEOL) circuitry portion including active circuitry fabricated on the FEOL circuitry portion and a back-end-of-the-line (BEOL) memory portion that is fabricated directly above and in contact with the FEOL circuitry portion such that the BEOL memory portion and the FEOL circuitry portion are an integrally formed unitary whole, 
 the BEOL memory portion including at least one memory layer that includes at least one of the two-terminal cross-point arrays, the plurality of conductive array lines of each two-terminal cross-point array are electrically coupled with at least a portion of the active circuitry.