Isolation with offset deep well implants

Abstract

A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

1 . A semiconductor structure comprising:
 at least one first transistor and at least one second transistor on a substrate;   a first shallow well implant below said first transistor;   a first deep well implant below said first shallow well implant;   a second shallow well implant below said second transistor; and   a second deep well implant below said second shallow well implant,   said first shallow well implant and said first deep well implant comprising a first-type impurity, and   said second shallow well implant and said second deep well implant comprising a second-type impurity, different than said first-type impurity.   
     
     
         2 . The semiconductor structure according to  claim 1 , said first shallow well implant contacting said second shallow well implant in said substrate, and said first deep well implant being spaced apart from said second deep well implant in said substrate. 
     
     
         3 . The semiconductor structure according to  claim 1 , said first shallow well implant having a width, relative to a top of said substrate, greater than a width of said first deep well implant, and said second shallow well implant having a width, relative to said top of said substrate, greater than a width of said second deep well implant. 
     
     
         4 . The semiconductor structure according to  claim 1 , said first-type impurity comprising a positive-type impurity (P-type impurity) and said second-type impurity comprising a negative-type impurity (N-type impurity). 
     
     
         5 . The semiconductor structure according to  claim 1 , further comprising shallow trench isolation regions between said first transistor and said second transistor. 
     
     
         6 . A semiconductor structure comprising:
 a substrate having a top surface;   at least one first transistor formed within and on said substrate; and   at least one second transistor formed within and on said substrate,   said first transistor comprising:
 a first gate oxide on said top surface of said substrate; 
 a first gate conductor on said first gate oxide; 
 first source and drain regions within said substrate adjacent said first gate conductor; 
 a first shallow well implant within said substrate below, relative to said top surface, said first gate conductors and said first source and drain regions; and 
 a first deep well implant within said substrate below, relative to said top surface, said first shallow well implant, said first deep well implant being at least five times deeper than said first shallow well implant, 
   said first deep well implant being centered below, relative to said top surface of said substrate, said first shallow well implant,   said first shallow well implant and said first deep well implant comprising a first-type impurity,   said second transistor comprising:
 a second gate oxide on said top surface of said substrate; 
 a second gate conductor on said second gate oxide; 
 second source and drain regions within said substrate adjacent said second gate conductor; 
 a second shallow well implant within said substrate below, relative to said top surface, said second gate conductors and said second source and drain regions; and 
 a second deep well implant within said substrate below, relative to said top surface, said second shallow well implant, said second deep well implants being at least five times deeper than said second shallow well implant, 
   said second deep well implant being centered below, relative to said top surface of said substrate, said second shallow well implant, and   said second shallow well implant and said second deep well implant comprising a second-type impurity.   
     
     
         7 . The semiconductor structure according to  claim 6 , said first shallow well implant contacting said second shallow well implant in said substrate, and said first deep well implant being spaced apart from said second deep well implant in said substrate. 
     
     
         8 . The semiconductor structure according to  claim 6 , said first shallow well implant having a width, relative to said top of said substrate, greater than a width of said first deep well implant, and said second shallow well implant having a width, relative to said top of said substrate, greater than a width of said second deep well implant. 
     
     
         9 . The semiconductor structure according to  claim 6 , said first-type impurity comprising a positive-type impurity (P-type impurity) and said second-type impurity comprising a negative-type impurity (N-type impurity). 
     
     
         10 . The semiconductor structure according to  claim 6 , further comprising shallow trench isolation regions between said first transistor and said second transistor. 
     
     
         11 . A semiconductor structure comprising:
 at least one first transistor and at least one second transistor on a substrate;   a first shallow well implant below said first transistor;   a first deep well implant centered below said first shallow well implant;   a second shallow well implant below said second transistor; and   a second deep well implant centered below said second shallow well implant,   said first shallow well implant and said first deep well implant comprising a first-type impurity, and   said second shallow well implant and said second deep well implant comprising a second-type impurity, different than said first-type impurity.   
     
     
         12 . The semiconductor structure according to  claim 11 , said first shallow well implant contacting said second shallow well implant in said substrate, and said first deep well implant being spaced apart from said second deep well implant in said substrate. 
     
     
         13 . The semiconductor structure according to  claim 11 , said first shallow well implant having a width, relative to said top of said substrate, greater than a width of said first deep well implant, and said second shallow well implant having a width, relative to said top of said substrate, greater than a width of said second deep well implant. 
     
     
         14 . The semiconductor structure according to  claim 11 , said first-type impurity comprising a positive-type impurity (P-type impurity) and said second-type impurity comprising a negative-type impurity (N-type impurity). 
     
     
         15 . The semiconductor structure according to  claim 11 , further comprising shallow trench isolation regions between said first transistor and said second transistor.