US2012043655A1PendingUtilityA1

Wafer-level package using stud bump coated with solder

Assignee: KHOR LILYPriority: Oct 23, 2008Filed: Nov 1, 2011Published: Feb 23, 2012
Est. expiryOct 23, 2028(~2.2 yrs left)· nominal 20-yr term from priority
H10W 74/47H10W 74/43H10W 72/9445H10W 72/07533H10W 72/07251H10W 72/07168H10W 72/07141H10W 72/5525H10W 72/5524H10W 72/5522H10W 72/01331H10W 72/01271H10W 72/01257H10W 72/01251H10W 72/01225H10W 72/01223H10W 72/01215H10W 72/952H10W 72/923H10W 72/255H10W 72/252H10W 72/245H10W 72/242H10W 72/223H10W 72/222H10W 72/221H10W 72/0112H10W 72/90H10W 72/075H10W 72/59H10W 72/29H10W 72/20H10W 72/012H10W 72/011H10W 74/014
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Claims

Abstract

A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor wafer package comprising:
 a semiconductor die having an upper surface;   a plurality of bonding pads formed on the semiconductor die;   a plurality of copper stud bumps corresponding to the plurality of bonding pads, each copper stud bumps being directly coupled to a bonding pad without under bump metallization between the stud bump and the bonding pad; and   an encapsulation layer overlying the semiconductor die while leaving an upper portion of each of the plurality of stud bumps exposed.   
     
     
         2 . The semiconductor wafer package set forth in  claim 1  further comprising a plurality of solder balls corresponding to the plurality of copper stud bumps, wherein each solder ball is attached to a respective one of the copper stud bumps. 
     
     
         3 . The semiconductor wafer package set forth in  claim 1  wherein each of the plurality of the stud bumps is a stacked stud bump comprising a plurality of copper bumps stacked on top of each other. 
     
     
         4 . The semiconductor wafer package set forth in  claim 1  wherein the package does not include underfill and has sufficient structural strength to meet standard board-level reliability metrics for a wafer-level package. 
     
     
         5 . A method of forming a stud bump on a semiconductor die using a wire bonding tool including a capillary having a feed hole for dispensing a wire, a bottom face and a chamfer surrounding the fee hole at the bottom face, the method comprising:
 providing a semiconductor wafer upon which the semiconductor die is formed;   prior to singulating the semiconductor wafer:
 (a) lowering the capillary towards the semiconductor wafer to allow an extruded portion of the wire from the feed hole to contact and form a first bond with a corresponding bond pad without breaking the wire; 
 (b) raising the capillary away from the semiconductor wafer while allowing the extruded portion of the wire to stay in contact with the bond pad without breaking the wire; 
 (c) offsetting the capillary from the first bond in a direction parallel to the upper surface of the semiconductor wafer; 
 (d) lowering the capillary so that the bottom face of the capillary contacts the stud bump and flattens a top surface of the stud bump; and 
 (e) moving the capillary away from the semiconductor die to separate the wire from the stud bump. 
   
     
     
         6 . The method of forming a stud bump as recited in  claim 5  wherein the step of lowering the capillary towards the semiconductor die further comprises applying mechanical force, heat, or ultrasonic energy to improve the bond between the extruded portion of the wire and the bond pad; wherein the step of offsetting the capillary comprises displacing a table upon which the semiconductor wafer is positioned during the wire bonding process; and wherein the step of lowering the capillary to flatten a top surface of the stud bump further comprises allowing an extended portion of the wire to form a second bond adjacent to the first bond where the stud bump is made up of the first and second bonds.

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