Memory Device Having Multiple Power Modes

Abstract

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

What is claimed is: 
     
         1 . A memory controller for controlling a memory device that includes a clock receiver, a command interface, and a data interface, the memory controller comprising:
 an interface to provide a command that specifies a write operation and data associated with the write operation after a programmable latency period transpires from when the command is provided; and   an interface to provide power mode information that controls transitions between a plurality of power modes, wherein for each power mode of the plurality of power modes, less power is consumed than the amount of power consumed during the write operation, the plurality of power modes comprising:
 a mode in which the clock receiver is on and the data interface is off; and 
 a mode in which the clock receiver is off and the data interface is off. 
   
     
     
         2 . The memory controller of  claim 1 , wherein:
 the mode in which the clock receiver is on and the data interface is off is a nap mode; and   the mode in which the clock receiver is off and the data interface is off is a powerdown mode.   
     
     
         3 . The memory controller of  claim 2 , wherein:
 during the nap mode, a locked loop circuit of the memory device is in a lower power consumption configuration than when the locked loop circuit is on; and   during the powerdown mode, the locked loop circuit of the memory device is off.   
     
     
         4 . The memory controller of  claim 1 , wherein the interface that provides the command is configured to provide, to the memory device via the command interface, address information associated with the write operation. 
     
     
         5 . The memory controller of  claim 4 , wherein the interface that provides the command is further configured to transmit a column control packet that includes both the command that specifies the write operation and the address information. 
     
     
         6 . The memory controller of  claim 1 , wherein the interface that provides the command is further configured to transmit a control packet containing the power mode information via a sideband interface to the memory device. 
     
     
         7 . A memory controller for controlling a memory device that includes a memory core, a clock receiver, a command interface, and a data interface, the memory controller comprising:
 an interface to provide a command that specifies a write operation during which the memory device inputs data, the write operation consuming an amount of power, the interface to provide the data, associated with the write operation, to the data interface, after a programmable latency period from when the command is provided; and   an interface to provide a signal that indicates to the memory device, a transition to an operating mode in which less power is consumed than the amount of power consumed during the write operation, wherein the transition is one of a plurality of transitions comprising:
 a transition in which the clock receiver is on, the command interface is turned off, and the data interface is turned off; and 
 a transition in which the clock receiver is turned off, the command interface is turned off, and the data interface is turned off. 
   
     
     
         8 . The memory controller of  claim 7 , wherein:
 the transition in which the clock receiver is on and the data interface is turned off is a transition from an active mode to a nap mode; and   the transition in which the clock receiver is turned off and the data interface is turned off is a transition from an active mode to a powerdown mode.   
     
     
         9 . The memory controller of  claim 8 , wherein:
 during the nap mode, a locked loop circuit of the memory device is in a lower power consumption configuration than when the locked loop circuit is on; and   during the powerdown mode, the locked loop circuit of the memory device is off.   
     
     
         10 . The memory controller of  claim 7 , further configured to provide, to the memory device, address information associated with the write operation. 
     
     
         11 . The memory controller of  claim 10 , further configured to transmit a column control packet that includes both the command that specifies the write operation and the address information. 
     
     
         12 . A memory controller for controlling a memory device that includes a clock receiver, a locked loop circuit, a command interface, and a data interface separate from the command interface, the memory controller comprising an interface configured to:
 provide, to the command interface, a command that specifies a write operation during which the memory device inputs data, the write operation consuming an amount of power;   provide the data, associated with the write operation, to the data interface, after a programmable latency period from when the command is provided; and   provide information that controls transitions between a plurality of power modes, the power modes comprising:
 a mode in which the clock receiver is on, the data interface is off and the locked loop circuit is on; and 
 a mode in which the clock receiver is off, the data interface is off, the locked loop circuit is off, and the command interface is off. 
   
     
     
         13 . The memory controller of  claim 12 , wherein:
 the mode in which the clock receiver is on, the data interface is off, and the locked loop circuit is on is a standby mode; and   the mode in which the clock receiver is off, the data interface is off, and the locked loop circuit is off is a powerdown mode.   
     
     
         14 . The memory controller of  claim 12 , further configured to provide, to the memory device, address information associated with the write operation. 
     
     
         15 . The memory controller of  claim 14 , further configured to transmit a column control packet that includes both the command that specifies the write operation and the address information. 
     
     
         16 . The memory controller of  claim 12 , further configured to transmit a control packet containing the power mode information via a sideband interface to the memory device. 
     
     
         17 . A memory controller for controlling a memory device comprising a memory core, a locked loop circuit, and a clock receiver circuit to receive an external clock signal, wherein the memory controller comprises one or more interfaces configured to:
 provide to a first interface of the memory device, a command that specifies a write operation;   after a programmable latency period transpires from when the command is provided to the first interface, provide to a second interface of the memory device that is separate from the first interface, write data associated with the write operation; and   provide power mode information to the memory device, wherein the power mode information specifies a mode selected from the group of modes comprising:
 a first mode in which the clock receiver, the first interface, and the second interface are off; 
 a second mode in which the clock receiver is on, the first interface and the second interface are off, and the locked loop circuit is in a first power state; and 
 a third mode in which the clock receiver is on, second interface is off, and the locked loop circuit is in a second power state. 
   
     
     
         18 . The memory controller of  claim 17 , wherein:
 the first mode is a powerdown mode;   the second mode is a nap mode; and   the third mode is a standby mode.   
     
     
         19 . The memory controller of  claim 17 , wherein:
 the first power state of the locked loop circuit is a low power mode; and   the second power state of the locked loop circuit is an on state.   
     
     
         20 . The memory controller of  claim 17 , further configured to provide, to the memory device, address information associated with the write operation. 
     
     
         21 . The memory controller of  claim 20 , further configured to transmit a column control packet that includes both the command that specifies the write operation and the address information. 
     
     
         22 . The memory controller of  claim 17 , further configured to transmit a control packet containing the power mode information to the memory device. 
     
     
         23 . A memory controller for controlling a memory device comprising a memory core, a locked loop circuit, and a clock receiver circuit to receive an external clock signal, wherein the memory controller comprises:
 an interface to provide:
 a command that specifies a write operation to a command interface of the memory device; and 
 after a programmable latency period transpires from when the command is provided to the command interface, provide to a data interface of the memory device, write data associated with the write operation; and 
   an interface to provide power mode information to the memory device, wherein the power mode information specifies a mode selected from the group of modes comprising:
 a first mode in which the clock receiver, the command interface, and the data interface are off; 
 a second mode in which the clock receiver is on, the command interface and the data interface are off, and the locked loop circuit is in a first power state; and 
 a third mode in which the clock receiver is on, the data interface is off, and the locked loop circuit is in a second power state. 
   
     
     
         24 . The memory controller of  claim 23 , wherein:
 the first mode is a powerdown mode;   the second mode is a nap mode; and   the third mode is a standby mode.   
     
     
         25 . The memory controller of  claim 23 , wherein:
 the first power state of the locked loop circuit is a low power mode; and   the second power state of the locked loop circuit is an on state.   
     
     
         26 . The memory controller of  claim 23 , further configured to provide, to the memory device, address information associated with the write operation. 
     
     
         27 . The memory controller of  claim 26 , further configured to transmit a column control packet that includes both the command that specifies the write operation and the address information. 
     
     
         28 . The memory controller of  claim 23 , further configured to transmit a control packet containing the power mode information via a sideband interface to the memory device.