Selective etch chemistries for forming high aspect ratio features and associated structures

Abstract

An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as Si x M y H z , where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x≧1, y≧0 and z≧0. The carbon species can be generated from a carbon compound, such as C α M β H γ , where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and α≧1, β≧0 and γ≧0. The oxygen species can be generated from an oxygen compound, such as O 2 , which can react with carbon to form a volatile compound.

We claim: 
     
         1 . A partially fabricated integrated circuit, comprising:
 an interlevel dielectric layer;   a plurality of features defined between openings in the interlevel dielectric layer, each feature having sidewalls defined by immediately neighboring openings in the interlevel dielectric layer, wherein a width at a top of each of the features defines a top width and a minimum width of the features defines a bow width, wherein a bow ratio of the top width to the bow width is less than or equal to about 1.4:1; and   a silicon and carbon-containing polymer film coating at least part of the sidewalls.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the polymer film is formed predominantly of carbon at an upper part of the sidewalls, and wherein the polymer film is formed predominantly of silicon at a lower part of the sidewalls. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the polymer film coats substantially an entirety of each of the sidewalls. 
     
     
         4 . The integrated circuit of  claim 1 , further comprising a masking layer overlying the interlevel dielectric layer, wherein the features and the openings extend into the masking layer. 
     
     
         5 . The integrated circuit of  claim 4 , wherein the silicon polymer film slopes laterally inward in the openings to form neck regions. 
     
     
         6 . The integrated circuit of  claim 5 , wherein the neck regions are disposed above a level of the interlevel dielectric and on a same level as the masking layer. 
     
     
         7 . The integrated circuit of  claim 4 , wherein the masking layer is a carbon-containing hard mask layer. 
     
     
         8 . The integrated circuit of  claim 7 , wherein the carbon-containing hard mask layer is formed of amorphous carbon. 
     
     
         9 . The integrated circuit of  claim 7 , wherein the carbon-containing hard mask layer is formed of photoresist. 
     
     
         10 . The integrated circuit of  claim 1 , wherein the bow ratio is less than or equal to about 1.3:1. 
     
     
         11 . The integrated circuit of  claim 10 , wherein the bow ratio is less than or equal to about 1.2:1. 
     
     
         12 . The integrated circuit of  claim 1 , wherein the openings have depth-to-width ratios greater than or equal to about 20:1 and a width less than or equal to about 100 nm. 
     
     
         13 . The integrated circuit of  claim 12 , wherein the depth-to-width ratios are greater than or equal to about 30:1. 
     
     
         14 . The integrated circuit of  claim 13 , wherein the depth-to-width ratios are greater than or equal to about 40:1. 
     
     
         15 . The integrated circuit of  claim 12 , wherein the width is about 80 nm or less. 
     
     
         16 . The integrated circuit of  claim 1 , wherein the openings have variations in widths of less than about 10 nm RMS, within 3 sigma. 
     
     
         17 . The integrated circuit of  claim 1 , wherein the interlevel dielectric layer is formed of silicon oxide. 
     
     
         18 . The integrated circuit of  claim 1 , wherein the interlevel dielectric layer is formed of a silicate glass. 
     
     
         19 . The integrated circuit of  claim 1 , wherein the openings are vias. 
     
     
         20 . The integrated circuit of  claim 1 , wherein the openings are trenches.