Integrated circuit and interconnect, and method of fabricating same

Abstract

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

1 . An integrated circuit comprising:
 at least one trench within a dielectric layer disposed on a substrate, the trench conformally coated with a liner and seed layer; and   an interconnect within the trench, the interconnect including a hard mask on sidewalls of the interconnect.   
     
     
         2 . The integrated circuit according to  claim 1 , wherein the hard mask comprises an anti-seeding conductive material selected from one of titanium nitride (TiN), tungsten (W), tantalum (Ta), and tantalum nitride (TaN). 
     
     
         3 . The integrated circuit according to  claim 1 , wherein the hard mask comprises a dielectric material selected from one of silicon nitride (Si 3 N 4 ), silicon carbide (SiC), and aluminum oxide (Al 2 O 3 ). 
     
     
         4 . The integrated circuit according to  claim 1 , wherein the interconnect comprises a material selected from one of copper, silver, and gold. 
     
     
         5 . The integrated circuit according to  claim 1 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm an wide. 
     
     
         6 . The integrated circuit according to  claim 1 , wherein the interconnect is an inductor or a transmission line. 
     
     
         7 . A method of fabricating an interconnect in an integrated circuit, the method comprising:
 conformally coating a trench with a liner and seed layer, the trench being within a dielectric layer disposed on a substrate;   depositing a hard mask on the liner and seed layer;   masking and patterning the trench to expose the hard mask;   removing exposed areas of the hard mask to expose areas of the liner and seed layer;   electrolytic metal plating the exposed areas of the liner and seed layer to form an interconnect; and   planarizing the interconnect with a top surface of the trench.   
     
     
         8 . The method of fabricating an interconnect according to  claim 7 , wherein the hard mask comprises a material selected from one of titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC) and aluminum oxide (Al 2 O 3 ). 
     
     
         9 . The method of fabricating an interconnect according to  claim 7 , wherein the interconnect comprises a material selected from one of copper, silver, and gold. 
     
     
         10 . The method of fabricating an interconnect according to  claim 7 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm wide. 
     
     
         11 . The method of fabricating an interconnect according to  claim 7 , wherein the planarizing step includes chemical-mechanical polishing the interconnect. 
     
     
         12 . The method of fabricating an interconnect according to  claim 7 , wherein the removing step includes plasma etching one or more times the exposed areas of the liner and seed layer. 
     
     
         13 . The method of fabricating an interconnect according to  claim 7 , wherein the electrolytic metal plating step includes plating the exposed areas of the liner and seed layer with a current density of approximately 1 A/cm 2  to approximately 15 A/cm 2  using a plating solution comprising a copper sulfate solution, a sulfuric acid solution, and a solution including chlorine ions. 
     
     
         14 . An inductor comprising:
 a core conductor including a top surface, a bottom surface, and sidewalls within a trench, the trench being within a dielectric layer on a substrate, and the trench having a liner and seed layer on a bottom and sidewalls of the trench; and   a hard mask on the sidewalls of the core conductor.   
     
     
         15 . The inductor according to  claim 14 , wherein the core conductor comprises a material selected from one of copper, silver, and gold. 
     
     
         16 . The inductor according to  claim 14 , wherein the core conductor is approximately 15 microns (μm) to approximately 150 μm wide. 
     
     
         17 . The inductor according to  claim 14 , wherein the hard mask comprises an anti-seeding conductive material selected from one of titanium nitride (TiN), tungsten (W), tantalum (Ta), and tantalum nitride (TaN). 
     
     
         18 . The inductor according to  claim 14 , wherein the hard mask comprises a dielectric material selected from one of silicon nitride (Si 3 N 4 ), silicon carbide (SiC), and aluminum oxide (Al 2 O 3 ). 
     
     
         19 . A method of fabricating an inductor, the method comprising:
 conformally coating a trench with a liner and seed layer, the trench being within a dielectric layer on a substrate;   depositing a hard mask on the liner and seed layer;   masking and patterning the trench to expose the hard mask;   removing exposed areas of the hard mask to expose areas of the liner and seed layer;   electrolytic metal plating the exposed areas of the liner and seed layer to form a core conductor; and   planarizing the core conductor, the hard mask, and the liner and seed layer with a top surface of the trench.   
     
     
         20 . The method of fabricating an inductor according to  claim 19 , wherein the hard mask comprises a material selected from one of titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum nitride (TaN), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), aluminum oxide (Al 2 O 3 ). 
     
     
         21 . The method of fabricating an inductor according to  claim 19 , wherein the core conductor comprises a material selected from one of copper, gold, and silver. 
     
     
         22 . The method of fabricating an inductor according to  claim 19 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm wide. 
     
     
         23 . The method of fabricating an inductor according to  claim 19 , wherein the planarizing step includes chemical-mechanical polishing the core conductor, the hard mask, and the liner and seed layer with a top surface of the trench. 
     
     
         24 . The method of fabricating an inductor according to  claim 19 , wherein the removing step includes plasma etching one or more times the exposed areas of the hard mask. 
     
     
         25 . The method of fabricating an inductor according to  claim 19 , wherein the electrolytic metal plating step includes plating the exposed areas of the liner and seed layer with a current density of approximately 1 A/cm 2  to approximately 15 A/cm 2  using a plating solution comprising a copper sulfate solution, a sulfuric acid solution, and a solution including chlorine ions.