Automated Bottom-Up and Top-Down Partitioned Design Synthesis

Abstract

An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

1 . A method for speeding up synthesis of a circuit design in a multiprocessing system, the method comprising:
 partitioning the circuit design into a plurality of compile points;   placing the compile points into a number of compile point groups, wherein the number of compile point groups is equal to a number of processors in the multiprocessing system;   assigning each one of the compile point groups to one of the processors; and   synthesizing, in parallel, each one of the compile point groups by the corresponding processor.