Inventor · disambiguated record
Gael Paul
Also filed as: PAUL GAEL · PAUL GAËL
14 granted patents·2 pending applications·82 citations·filing 2003–2018
91Inventor score
Top patents by PatentIndex Score
16 records- 0184US8307315B2Methods and apparatuses for circuit design and optimizationADYA SAURABH·Filed 2009·Granted Nov 6, 2012·15 cites·30 claims
- 0282US7500205B2Skew reduction for generated clocksSYNOPSYS INC·Filed 2006·Granted Mar 3, 2009·12 cites·51 claims
- 0380US8161435B2Reset mechanism conversionMANOHAR RAJIT·Filed 2009·Granted Apr 17, 2012·8 cites·24 claims
- 0478US8443315B2Reset mechanism conversionMANOHAR RAJIT·Filed 2012·Granted May 14, 2013·4 cites·19 claims
- 0577US8301933B2Multi-clock asynchronous logic circuitsMANOHAR RAJIT·Filed 2009·Granted Oct 30, 2012·8 cites·28 claims
- 0674US11562050B2System and method for licensing and for measuring use of an IP blockCENTRE NAT RECH SCIENT·Filed 2018·Granted Jan 24, 2023·2 cites·9 claims
- 0772US7982502B2Asynchronous circuit representation of synchronous circuit with asynchronous inputsACHRONIX SEMICONDUCTOR CORP·Filed 2009·Granted Jul 19, 2011·5 cites·12 claims
- 0870US8104004B2Logic performance in cyclic structuresPAUL GAEL·Filed 2008·Granted Jan 24, 2012·9 cites·29 claims
- 0967US8234607B2Token enhanced asynchronous conversion of synchonous circuitsEKANAYAKE VIRANTHA·Filed 2009·Granted Jul 31, 2012·4 cites·10 claims
- 1064US9280632B2Methods and apparatuses for circuit design and optimizationSYNOPSIS INC·Filed 2012·Granted Mar 8, 2016·1 cites·20 claims
- 1164US8082138B1Automated bottom-up and top-down partitioned design synthesisBAKSHI SMITA·Filed 2003·Granted Dec 20, 2011·12 cites·54 claims
- 1262US8661378B2Asychronous system analysisMANOHAR RAJIT·Filed 2009·Granted Feb 25, 2014·2 cites·26 claims
- 1356US10296689B2Automated bottom-up and top-down partitioned design synthesisSYNOPSYS INC·Filed 2014·Granted May 21, 2019·0 cites·20 claims
- 1452US2016188774A1Circuit Design and OptimizationSYNOPSYS INC·Filed 2016·Application pending·0 cites
- 1545US2012089956A1Automated Bottom-Up and Top-Down Partitioned Design SynthesisBAKSHI SMITA·Filed 2011·Application pending·0 cites
- 1640US11023621B2System and method for authenticating and IP licensing of hardware modulesUNIV MONTPELLIER·Filed 2016·Granted Jun 1, 2021·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →