US2016188774A1PendingUtilityA1
Circuit Design and Optimization
Est. expiryJan 30, 2029(~2.6 yrs left)· nominal 20-yr term from priority
G06F 30/30G06F 17/5072G06F 17/5031G06F 30/392G06F 2119/12G06F 30/337G06F 30/398G06F 30/3312
52
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Claims
Abstract
A method implemented on a data processing system for circuit design is described. The method comprises identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via nets, and determining whether timing of an element of a particular first portion is sensitive to degradation of a signal from a net associated with the particular first portion. In one embodiment, the method further comprises reporting the determination.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method implemented on a data processing system for circuit design, the method comprising:
identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via nets; determining whether timing of an element of a particular first portion is sensitive to degradation of a signal from a net associated with the particular first portion; reporting the determination.
2 . The method of claim 1 , further comprising:
in response to a determination of sensitivity to degradation, the reporting including a recommendation to isolate the element.
3 . The method of claim 1 , further comprising:
receiving user input to select one of the first portions to assign in a block in a floor plan; and floor planning the corresponding one of the first portions in the block according to the user input.
4 . The method of claim 1 , further comprising:
receiving input to select one of the first portions to re-assign in a block in a floor plan; and floor planning the corresponding one of the first portions in the block according to the input.
5 . The method of claim 1 , further comprising:
identifying a plurality of functional modules of the design of the circuit; and identifying critical paths interconnecting the plurality of functional modules, wherein reporting the determination includes presenting the critical paths grouped according to the first portions.
6 . The method of claim 5 , wherein one or more of the nets in the plurality of the first portions comprises critical paths interconnecting the functional modules.
7 . The method of claim 1 , wherein the timing of the element is visualized in a cross-probe to other views of the circuit design.
8 . A method implemented on a data processing system for circuit design, the method comprising:
identifying a first portion of a design of a circuit, the first portion containing a set of elements interconnected via nets; and isolating a timing dependency of the first portion on a net connected to an element of the first portion.
9 . The method of claim 8 , wherein the timing dependency is visualized in a cross-probe to other views of the circuit design.
10 . The method of claim 9 , wherein the cross-probe is visualized as an RTL view of the circuit design.
11 . The method of claim 9 , wherein the cross-probe is visualized as an HDL view of the circuit design.
12 . The method of claim 9 , wherein the cross-probe is visualized as a three-dimensional graph of the circuit design.
13 . The method of claim 8 , wherein each of the first portions is a single critical-net connected graph of elements.
14 . The method of claim 9 , wherein the cross-probe visualized in a second view shows elements of critical paths in the corresponding one of the first portions.
15 . The method of claim 8 , wherein each of the first portions is a single critical-net connected graph of elements.
16 . A method implemented on a data processing system for circuit design, the method comprising:
identifying a first portion of a design of a circuit, the first portion containing a set of elements interconnected via nets; and isolating a timing dependency of the first portion on a net connected to an element of the first portion.
17 . The method of claim 16 , wherein the isolating comprises:
inserting a buffer on the net as part of the first portion.
18 . The method of claim 16 , wherein the isolating comprises:
replicating a drive element of the non-critical net as part of the first portion.
19 . The method of claim 16 , wherein the net is a net driving an element of the first portion and the isolating is performed automatically in response to identifying the first portion.
20 . The method of claim 19 , further comprising:
determining whether timing of the element of the first portion is sensitive to capacitive load; wherein the isolating is performed when the element is sensitive to capacitive load.Cited by (0)
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