Forming an extremely thin semiconductor-on-insulator (etsoi) layer

Abstract

Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

1 . A method comprising:
 providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI);   forming a mask over a first one of the plurality of SOI layer regions, the mask exposing at least one of the SOI layer regions distinct from the first region;   amorphizing the at least one exposed SOI layer region by implanting the at least one exposed SOI layer region with an implant species;   removing the mask after the amorphizing; and   removing a portion of the amorphized SOI layer to form a recess in the amorphized SOI layer.   
     
     
         2 . The method of  claim 1 , wherein the wafer further includes a plurality of STIs, wherein the recess is formed between the plurality of STIs. 
     
     
         3 . The method of  claim 1 , wherein the implant species includes at least one of silicon, germanium and xenon. 
     
     
         4 . The method of  claim 1 , wherein the implanting is performed at an energy level less than approximately 60 KeV, and wherein the implanting reaches a depth of the SOI wafer of approximately 400-500 Angstroms. 
     
     
         5 . The method of  claim 1 , wherein the implant species is xenon, and wherein the implant energy is approximately 20-30 KeV. 
     
     
         6 . The method of  claim 1 , wherein the removing of the portion of the amorphized SOI layer includes chemical-mechanical polishing (CMP). 
     
     
         7 . The method of  claim 1 , wherein the removing of the portion of the amorphized SOI layer includes reactive ion etching (RIE). 
     
     
         8 . The method of  claim 1 , wherein the plurality of SOI layer regions includes at least three distinct SOI layer regions having different thicknesses. 
     
     
         9 . The method of  claim 8 , wherein the three distinct SOI layer regions include a first region having a substantially uniform thickness, a second region having a substantially non-uniform thickness, and a third region having a substantially uniform thickness less than the first region. 
     
     
         10 . The method of  claim 1 , wherein the first one of the plurality of SOI layer regions has a thickness greater than the exposed SOI layer region. 
     
     
         11 . An extra-thin semiconductor-on-insulator (ETSOI) layer comprising:
 a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses;   at least one recess located within the distinct SOI regions; and   an oxide cap over the at least one recess,   wherein the at least three different thicknesses include: a first thickness of approximately 60-100 angstroms, a second thickness of approximately 25-60 angstroms, and a third thickness of approximately 5-25 angstroms.   
     
     
         12 . The ETSOI layer of  claim 11 , further comprising a raised source/drain region located between at least two of the plurality of STI, the raised source/drain region located within the region having a thickness of approximately 25-60 angstroms.