Method and apparatus for performing an operation with a plurality of sub-operations in a configurable ic

Abstract

Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, reconfigures a single logic circuit to perform one of the sub-operations to generate a partial result of the mathematical operation. In some embodiments, the logic circuit is reconfigured by receiving a first set of configuration data that cause the logic circuit to reconfigure to perform a first sub-operation operation and a second set of configuration data that cause the logic circuit to reconfigure to perform a second sub-operation. In some embodiments, the logic circuit receives different inputs based on the value of the bits being examined. In some embodiments, the mathematical operation is multiplication and the sub-operations are addition and subtraction.

1 - 15 . (canceled) 
     
     
         16 . An integrated circuit (“IC”) comprising:
 a reconfigurable logic circuit that receives a plurality of inputs; 
 a signal generator for generating a selection signal based on a set of user signals; and 
 a selection circuit for supplying one of a plurality of configuration data sets to the reconfigurable logic circuit based on the selection signal, wherein the reconfigurable logic circuit performs different operations on the plurality of inputs based on supplied configuration data sets. 
 
     
     
         17 . The IC of  claim 16 , wherein a user signal is a signal that is determined at least partially based on a set of inputs to the IC. 
     
     
         18 . The IC of  claim 17 , wherein the set of inputs to the IC is not stored in configuration storages within the IC. 
     
     
         19 . The IC of  claim 16 , wherein a user signal is a signal that is determined based on a current state of the IC, wherein the current state is determined based on configuration data received by the IC, inputs to the IC, and a prior state of the IC. 
     
     
         20 . The IC of  claim 16 , wherein the plurality of inputs comprise first and second inputs, wherein the plurality of configuration data sets comprise a first configuration data set for configuring the reconfigurable logic circuit to perform an XOR operation between the first and second inputs, a second configuration data set for configuring the reconfigurable logic circuit to perform an AND operation between the second input and complement of the first input, a third configuration data set for configuring the reconfigurable logic circuit to perform an OR operation between the first input and complement of the second input, and a fourth configuration data set for configuring the reconfigurable logic circuit to perform an AND operation between the first and second input. 
     
     
         21 . The IC of  claim 20 , wherein the selection circuit supplies one of the first, second, third, and fourth configuration data sets to the reconfigurable logic circuit based on the selection signal. 
     
     
         22 . The IC of  claim 20 , wherein, based on the configuration data set supplied to the reconfigurable logic circuit, the reconfigurable logic circuit performs one of the XOR operation between the first and second inputs, the AND operation between the second input and complement of the first input, the OR operation between the first input and complement of the second input, and the AND operation between the first and second input to perform an encryption operation. 
     
     
         23 . The IC of  claim 22 , wherein the encryption operation is MD5 encryption operation. 
     
     
         24 . The IC of  claim 16 , wherein the user signal is non-repetitive. 
     
     
         25 . A method for operating a reconfigurable circuit of an integrated circuit (“IC”), the method comprising:
 generating a user-design signal within the IC; 
 when the user-design signal has a first value, performing a first set of operations by the reconfigurable circuit based on a first set of configuration data sets; and 
 when the user-design signal has a second value, performing a second set of operations by the reconfigurable circuit based on a second set of configuration data sets, 
 wherein the first and second set of configuration data sets are different sub-sets of a plurality of configuration data sets stored in a set of configuration storage elements within the IC for the reconfigurable circuit. 
 
     
     
         26 . The method of  claim 25 , wherein the user-design signal is a signal that is determined at least partially based on a set of inputs to the IC. 
     
     
         27 . The method of  claim 26 , wherein the set of inputs to the IC is not stored in the set of configuration storage elements. 
     
     
         28 . The method of  claim 25 , wherein a user-design signal is a signal that is determined based on a current state of the IC, wherein the current state is determined based on configuration data received by the IC, inputs to the IC, and a prior state of the IC. 
     
     
         29 . The method of  claim 25  further comprising performing an operation before performing one of the first and second set of operations. 
     
     
         30 . The method of  claim 25 , wherein each configuration data set defines a set of operations that the reconfigurable circuit performs. 
     
     
         31 . The method of  claim 25 , wherein the user-design signal is non-repetitive. 
     
     
         32 . The method of  claim 25  further comprising supplying one of the first and second set of configuration data sets to the reconfigurable circuit by a selection circuit based on the user-design signal. 
     
     
         33 . The method of  claim 32  further comprising generating a selection signal by a signal generator for the selection circuit based on the user-design signal to conditionally supply configuration data sets to the reconfigurable circuit. 
     
     
         34 . The method of  claim 33  further comprising supplying a plurality of period clock signals from a global clock generator to the signal generator. 
     
     
         35 . The method of  claim 33 , wherein the signal generator generates sub-cycle signals to drive the reconfigurable circuit.