Chip package structure and manufacturing methods thereof

Abstract

A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit.

1 . A semiconductor package, comprising:
 a chip having an active surface;   a pre-patterned structure disposed adjacent to lateral surfaces of the chip, the pre-patterned structure having a contact on a surface oriented in the same direction as the active surface;   a redistribution layer that electrically connects the active surface of the chip with the contact; and   a filling material that covers portions of the chip, exposing the active surface and the pre-patterned structure.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the active surface of the chip is substantially co-planar with a surface of the pre-patterned structure. 
     
     
         3 . The semiconductor package of  claim 2 , wherein the redistribution layer is disposed adjacent to the active surface of the chip and the substantially co-planar surface of the pre-patterned structure. 
     
     
         4 . The semiconductor package of  claim 1 , wherein the pre-patterned structure includes interconnected trace layers. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the filling material covers the lateral surfaces of the chip. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the filling material substantially covers a surface of the pre-patterned structure and has an opening to expose a contact on the surface of the pre-patterned structure. 
     
     
         7 . The semiconductor package of  claim 1 , further including a second redistribution layer disposed adjacent to an inactive surface of the chip and electrically connected to the pre-patterned structure. 
     
     
         8 . A semiconductor package, comprising:
 a chip having an active surface;   an interposer disposed adjacent to a lateral surface of the chip, the interposer having a contact on a surface oriented in the same direction as the active surface;   a redistribution layer that electrically connects the active surface of the chip with the contact; and   a filling material that covers portions of the chip, exposing the active surface and the pre-patterned structure.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the active surface of the chip is substantially co-planar with a surface of the interposer. 
     
     
         10 . The semiconductor package of  claim 9 , wherein the redistribution layer is disposed adjacent to the active surface of the chip and the substantially co-planar surface of the interposer. 
     
     
         11 . The semiconductor package of  claim 8 , wherein the interposer includes interconnected trace layers. 
     
     
         12 . The semiconductor package of  claim 8 , wherein the filling material covers the lateral surfaces of the chip. 
     
     
         13 . The semiconductor package of  claim 8 , wherein the filling material substantially covers a surface of the interposer and has an opening to expose a contact on the surface of the interposer. 
     
     
         14 . The semiconductor package of  claim 8 , further including a second redistribution layer disposed adjacent to an inactive surface of the chip and electrically connected to the interposer. 
     
     
         15 . The semiconductor package of  claim 14 , wherein the filling material has an opening wherein the second redistribution layer is electrically connected to the interposer through the opening. 
     
     
         16 . The semiconductor package of  claim 8 , further comprising an adhesive layer disposed on a surface of the filling material. 
     
     
         17 . The semiconductor package of  claim 16 , further comprising a protection layer disposed on the adhesive layer, wherein the adhesive layer connects the protection layer to the surface of the filling material. 
     
     
         18 . A method of forming a semiconductor package, comprising:
 providing a chip;   providing a plurality of separate pre-patterned structures, wherein each of the plurality of separate pre-patterned structures includes a circuit;   providing a carrier;   disposing the plurality of separate pre-patterned structures and the chip on the carrier such that the plurality of separate pre-patterned structures are positioned adjacent to lateral sides of the chip; and   disposing a filling material around the chip and the plurality of separate pre-patterned structures, exposing an active surface of the chip.   
     
     
         19 . The method of  claim 18 , wherein each of the plurality of separate pre-patterned structures includes multiple interconnected trace layers. 
     
     
         20 . The method of  claim 18 , further comprising:
 creating a slot on a surface of each of the separate pre-patterned structures to expose the circuit of the pre-patterned structure; and   forming a redistribution layer disposed adjacent to the active surface of the chip and substantially co-planar surfaces of the plurality of the separate pre-patterned structures, wherein the redistribution layer electrically connects the chip and the circuit in each of the plurality of separate pre-patterned structures through the slots.