US2012126399A1PendingUtilityA1

Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry

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Assignee: LIN CHARLES W CPriority: Nov 22, 2010Filed: Aug 3, 2011Published: May 24, 2012
Est. expiryNov 22, 2030(~4.4 yrs left)· nominal 20-yr term from priority
H05K 1/186H05K 1/0207H10W 90/724H10W 90/722H10W 74/00H10W 72/9413H10W 72/07338H10W 72/01257H10W 72/01235H10W 72/01223H10W 72/944H10W 72/874H10W 72/354H10W 72/352H10W 72/325H10W 72/252H10W 72/241H10W 72/073H10W 72/29H10W 70/099H10W 70/093H10W 70/60H10W 70/09H10W 90/00H10W 74/01H10W 70/635H10W 70/614H10W 42/20H10W 40/228H10W 70/682H10W 74/114
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Claims

Abstract

A semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device.

Claims

exact text as granted — not AI-modified
1 . A thermally enhanced semiconductor assembly, comprising:
 a heat spreader that includes a bump, a base and a flange, wherein (i) the bump is adjacent to the base and the flange, is integral with the flange, extends from the base in a first vertical direction and extends from the flange in a second vertical direction opposite the first vertical direction, (ii) the base extends from and covers the bump in the second vertical direction and extends laterally from the bump in lateral directions orthogonal to the vertical directions, (iii) the flange extends laterally from the bump and is spaced from the base, and (iv) a cavity in the bump faces in the first vertical direction, is covered by the bump in the second vertical direction, is spaced from the base by the bump and has an entrance at the flange;   a substrate that includes an aperture;   an adhesive that includes an opening, wherein the bump extends into the opening and the aperture, and the adhesive contacts the bump, the base, the flange and the substrate, is sandwiched between the bump and the substrate, between the flange and the substrate and between the base and the flange and extends laterally from the bump to peripheral edges of the assembly;   a semiconductor device that includes contact pads and is mounted on the bump and extends into the cavity;   a first dielectric layer that extends from the semiconductor device and the flange in the first vertical direction and includes first via openings aligned with the contact pads; and   first conductive traces that extend from the first dielectric layer in the first vertical direction and extend laterally on the first dielectric layer and extend through the first via openings in the second vertical direction to the contact pads to provide electrical connections for the semiconductor device.   
     
     
         2 . The assembly of  claim 1 , wherein the cavity extends across most of the bump in the vertical and lateral directions. 
     
     
         3 . The assembly of  claim 1 , wherein the semiconductor device is connected to the bump using a die attach that is located within the cavity. 
     
     
         4 . The assembly of  claim 1 , wherein the bump has an irregular thickness characteristic of stamping. 
     
     
         5 . The assembly of  claim 1 , wherein the bump includes a first bent corner adjacent to the base and a second bent corner adjacent to the flange. 
     
     
         6 . The assembly of  claim 1 , wherein the bump is coplanar with the adhesive at the base. 
     
     
         7 . The assembly of  claim 1 , wherein the bump and the flange contact and are sandwiched between and space and separate the adhesive and the first dielectric layer. 
     
     
         8 . The assembly of  claim 1 , wherein the base has a first thickness where it is adjacent to the bump, a second thickness where it is adjacent to the substrate that is larger than the first thickness and a flat surface that faces in the second vertical direction. 
     
     
         9 . The assembly of  claim 1 , wherein the adhesive has a first thickness where it is adjacent to the flange and a second thickness where it is adjacent to the bump that is different from the first thickness. 
     
     
         10 . The assembly of  claim 1 , wherein the first dielectric layer further extends into the cavity. 
     
     
         11 . The assembly of  claim 1 , wherein the first via openings are aligned with the flange and the contact pads, and the first conductive traces extend through the first via openings in the second vertical direction to the flange and the contact pads to provide electrical connections for the flange and the contact pads. 
     
     
         12 . The assembly of  claim 1 , wherein the base, the substrate and the first dielectric layer extend to peripheral edges of the assembly. 
     
     
         13 . The assembly of  claim 12 , wherein the flange extends to peripheral edges of the assembly. 
     
     
         14 . The assembly of  claim 1 , further including:
 a second dielectric layer that extends from the first dielectric layer and the first conductive traces in the first vertical direction and includes second via openings aligned with the first conductive traces; and   second conductive traces that extend from the second dielectric layer in the first vertical direction and extend laterally on the second dielectric layer and extend through the second via openings in the second vertical direction to provide electrical connections for the first conductive traces.   
     
     
         15 . A thermally enhanced semiconductor assembly, comprising:
 a heat spreader that includes a bump, a base and a flange, wherein (i) the bump is adjacent to the base and the flange, is integral with the flange, extends from the base in a first vertical direction and extends from the flange in a second vertical direction opposite the first vertical direction, (ii) the base extends from and covers the bump in the second vertical direction and extends laterally from the bump in lateral directions orthogonal to the vertical directions, (iii) the flange extends laterally from the bump and is spaced from the base, and (iv) a cavity in the bump faces in the first vertical direction, is covered by the bump in the second vertical direction, is spaced from the base by the bump and has an entrance at the flange;   an adhesive that includes an opening, wherein the bump extends into the opening, and the adhesive contacts the bump, the base and the flange, laterally covers and surrounds and conformally coats a sidewall of the bump and extends laterally from the bump to peripheral edges of the assembly;   a semiconductor device that includes contact pads and is mounted on the bump and extends into the cavity;   a first dielectric layer that extends from the semiconductor device and the flange in the first vertical direction and includes first via openings aligned with the contact pads; and   first conductive traces that extend from the first dielectric layer in the first vertical direction and extend laterally on the first dielectric layer and extend through the first via openings in the second vertical direction to the contact pads to provide electrical connections for the semiconductor device.   
     
     
         16 . The assembly of  claim 15 , wherein the cavity extends across most of the bump in the vertical and lateral directions. 
     
     
         17 . The assembly of  claim 15 , wherein the semiconductor device is connected to the bump using a die attach that is located within the cavity. 
     
     
         18 . The assembly of  claim 15 , wherein the bump has an irregular thickness characteristic of stamping. 
     
     
         19 . The assembly of  claim 15 , wherein the bump includes a first bent corner adjacent to the base and a second bent corner adjacent to the flange. 
     
     
         20 . The assembly of  claim 15 , wherein the bump is coplanar with the adhesive at the base. 
     
     
         21 . The assembly of  claim 15 , wherein the bump and the flange contact and are sandwiched between and space and separate the adhesive and the first dielectric layer. 
     
     
         22 . The assembly of  claim 15 , wherein the base has a first thickness where it is adjacent to the bump, a second thickness where it is adjacent to the adhesive that is larger than the first thickness and a flat surface that faces in the second vertical direction. 
     
     
         23 . The assembly of  claim 15 , wherein the adhesive has a first thickness where it is adjacent to the flange and a second thickness where it is adjacent to the bump that is different from the first thickness. 
     
     
         24 . The assembly of  claim 15 , wherein the first dielectric layer further extends into the cavity. 
     
     
         25 . The assembly of  claim 15 , wherein the first via openings are aligned with the flange and the contact pads, and the first conductive traces extend through the first via openings in the second vertical direction to the flange and the contact pads to provide electrical connections for the flange and the contact pads. 
     
     
         26 . The assembly of  claim 15 , wherein the base and the first dielectric layer extend to peripheral edges of the assembly. 
     
     
         27 . The assembly of  claim 26 , wherein the flange extends to peripheral edges of the assembly. 
     
     
         28 . The assembly of  claim 15 , further including:
 a second dielectric layer that extends from the first dielectric layer and the first conductive traces in the first vertical direction and includes second via openings aligned with the first conductive traces; and   second conductive traces that extend from the second dielectric layer in the first vertical direction and extend laterally on the second dielectric layer and extend through the second via openings in the second vertical direction to provide electrical connections for the first conductive traces.

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