Wafer-to-wafer stack with supporting pedestal

Abstract

A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.

1 . A method for stacking a three dimensional wafer structure, comprising the steps of:
 providing a first wafer;   disposing a second wafer above the first wafer;   forming a supporting structure on the first wafer;   forming plural interconnecting vias running through the second wafer for electrically interconnecting opposite sides of the second wafer; and   bonding the first and the second wafers for completing the three dimensional wafer structure.   
     
     
         2 . A method according to  claim 2 , wherein the plural interconnecting vias are formed by one of processes selected from a group consisting of UV laser process, CO2 laser process, and chemical etching process. 
     
     
         3 . A method according to  claim 1 , further comprising a step of filling up a part of the interconnecting vias with an electrically conductive material for electrically interconnecting both sides of the second wafer. 
     
     
         4 . A method according to  claim 3 , further comprising a step of forming an insulator layer around side walls of the part of the interconnecting vias. 
     
     
         5 . A method according to  claim 3 , further comprising a step of forming an electrically conductive layer on the second wafer.