Structure with isotropic silicon recess profile in nanoscale dimensions

Abstract

A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

1 . A semiconductor structure comprising:
 a trench located in a semiconductor material layer; and   an adsorbed fluorine layer located on vertical surfaces of said trench, while horizontal surfaces of said trench do not have adsorbed fluorine thereupon.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said semiconductor material layer comprises silicon. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein said adsorbed fluorine layer is a monolayer of fluorine atoms that are atomically bonded to an underlying semiconductor material in said semiconductor material layer. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising a gate structure located on said semiconductor material layer, said gate structure including a gate dielectric, a gate conductor, and a gate spacer. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein said adsorbed fluorine layer contiguously extends over a vertical portion of a surface of said gate spacer. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein said vertical surfaces define a periphery of said trench, and said adsorbed fluorine layer contiguously covers all of said vertical surfaces. 
     
     
         7 . The semiconductor structure of  claim 6 , further comprising gate spacers having outer sidewalls that adjoin upper portions of said vertical surfaces. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein said adsorbed fluorine layer contiguously covers a lower portion of each of said outer sidewalls of said gate spacers. 
     
     
         9 . The semiconductor structure of  claim 1 , further comprising a buried insulator layer located underneath said semiconductor material layer. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein a bottommost surface of said trench is vertically spaced from a topmost surface of said buried insulator layer. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising at least one gate spacer located on a top surface of said semiconductor material layer. 
     
     
         12 . The semiconductor structure of  claim 11 , wherein said at least one gate spacer comprises:
 a first gate spacer located at one side of said trench and not overlying said trench; and   a second gate spacer located at another side of said trench and not overlying said trench.   
     
     
         13 . The semiconductor structure of  claim 11 , wherein a periphery of said vertical surfaces of said trench coincides with outer peripheries of said at least one gate spacer at which outer sidewalls of said at least one gate spacer contact said top surface of said semiconductor material layer. 
     
     
         14 . The semiconductor structure of  claim 11 , wherein each of said at least one gate spacer laterally surrounds a gate structure comprising a vertical stack, from bottom to top, of a gate dielectric, a gate conductor, and a dielectric cap. 
     
     
         15 . The semiconductor structure of  claim 11 , wherein said at least one gate spacer comprises a material selected from silicon nitride, silicon oxynitride, and a combination of silicon oxide and silicon nitride. 
     
     
         16 . The semiconductor structure of  claim 1 , wherein said semiconductor material layer comprises a semiconductor material selected from silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. 
     
     
         17 . The semiconductor structure of  claim 1 , wherein said semiconductor material layer comprises a single crystalline material. 
     
     
         18 . The semiconductor structure of  claim 1 , wherein a bottom surface of said trench has a crystallographic orientation that provides a greater oxidation rate for a semiconductor material of said semiconductor material layer than crystallographic orientations of said vertical surfaces of said trench. 
     
     
         19 . The semiconductor structure of  claim 18 , wherein said semiconductor material layer is a single crystalline silicon layer and said bottom surface of said trench has a <111> orientation, and said vertical surfaces of said trench has a <110> orientation. 
     
     
         20 . The semiconductor structure of  claim 18 , wherein said semiconductor material layer is a single crystalline silicon layer and said bottom surface of said trench has a <110> orientation, and said vertical surfaces of said trench has a <100> orientation.