Method for fabricating mos transistor

Abstract

The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

1 . A method for fabricating a MOS transistor, comprising:
 providing a substrate having thereon a gate structure;   forming a recess in the substrate on each side of the gate structure;   forming a transitional layer covering the recess;   performing a pre-epitaxial clean process to remove the transitional layer; and   performing an epitaxial growth process to grow an embedded SiGe layer in the recess.   
     
     
         2 . The method according to  claim 1 , wherein said forming the recess in the substrate comprises:
 depositing a silicon nitride layer on the gate structure; and   etching the silicon nitride layer and the substrate, thereby forming a disposable silicon nitride spacer on each sidewall of the gate structure.   
     
     
         3 . The method according to  claim 1 , wherein said forming the recess in the substrate comprises:
 depositing forming a first spacer on a sidewall of the gate structure;   depositing a silicon nitride layer on the first spacer; and   etching the silicon nitride layer and the substrate, thereby forming a disposable silicon nitride spacer on each sidewall of the gate structure.   
     
     
         4 . The method according to  claim 1 , wherein before performing an epitaxial growth process, the method further comprises subjecting the substrate to a pre-bake process. 
     
     
         5 . The method according to  claim 2  further comprising removing the disposable silicon nitride spacer. 
     
     
         6 . The method according to  claim 3  further comprising removing the disposable silicon nitride spacer. 
     
     
         7 . The method according to  claim 1  wherein the gate structure comprises a gate dielectric layer, a polysilicon layer and a hard mask. 
     
     
         8 . The method according to  claim 3  wherein after forming the first spacer, the method further comprises performing a lightly doped drain (LDD) implant to form an LDD region in the substrate on both sides of the gate structure. 
     
     
         9 . The method according to  claim 3  wherein the first spacer comprises silicon oxide spacer. 
     
     
         10 . The method according to  claim 3  wherein the disposable silicon nitride spacer is formed by using hexachlorodisilane (HCD) as precursor. 
     
     
         11 . The method according to  claim 3  wherein the transitional layer is in contact with the disposable silicon nitride spacer. 
     
     
         12 . The method according to  claim 1  wherein the transitional layer comprises silicon oxide layer. 
     
     
         13 . The method according to  claim 1  wherein the transitional layer is a material layer capable of adsorbing, absorbing or bonding chlorine atoms. 
     
     
         14 . The method according to  claim 1  wherein the pre-epitaxial clean process utilizes diluted HF to completely remove the transitional layer. 
     
     
         15 . The method according to  claim 4  wherein the pre-bake process is carried out at a temperature of at least 800° C. 
     
     
         16 . The method according to  claim 1  wherein the transitional layer covers the gate structure.