Stack packages having fastening element and halogen-free inter-package connector

Abstract

A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

1 . A stack package, comprising:
 a lower package comprising a lower package substrate and a lower semiconductor chip disposed on the lower package substrate;   an upper package comprising an upper package substrate and an upper semiconductor chip disposed on the upper package substrate;   a fastening element disposed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate; and   a halogen-free inter-package connector to connect a top surface of the lower package substrate to the bottom surface of the upper package substrate.   
     
     
         2 . The package of  claim 1 , further comprising an air space disposed between the fastening element and the inter-package connector. 
     
     
         3 . The package of  claim 1 , wherein the fastening element is in direct contact with the top surface of the lower semiconductor chip and the bottom surface of the upper package substrate. 
     
     
         4 . The package of  claim 1 , wherein the fastening element comprises a thermosetting resin. 
     
     
         5 . The package of  claim 1 , wherein the lower semiconductor package comprises a lower molding material surrounding a side surface of the lower semiconductor chip and a side surface of the inter-package connector. 
     
     
         6 . The package of  claim 5 , wherein the lower molding material covers a part of the top surface of the lower semiconductor chip. 
     
     
         7 . The package of  claim 6 , wherein the lower molding material exposes a part of the top surface of the lower semiconductor chip. 
     
     
         8 . The package of  claim 5 , wherein the fastening element is disposed on a part of the top surface of the lower semiconductor chip and a part of a top surface of the lower molding material. 
     
     
         9 . The package of  claim 5 , wherein the lower molding material surrounds a lower side surface of the inter-package connector, and exposes an upper side surface of the inter-package connector. 
     
     
         10 . The package of  claim 1 , wherein the halogen-free inter-package connector comprises a solder material. 
     
     
         11 . The package of  claim 1 , wherein the halogen-free inter-package connector comprises a pot shape in which a volume of an upper part is greater than a volume of the lower part. 
     
     
         12 . The package of  claim 1 , wherein the halogen-free inter-package connector comprises a lower inter-package connector and an upper inter-package connector. 
     
     
         13 . The package of  claim 12 , wherein the lower inter-package connector has a smaller volume than the upper inter-package connector. 
     
     
         14 . The package of  claim 12 , wherein the halogen-free inter-package connector further comprises an intermediate inter-package connector disposed between the lower inter-package connector and the upper inter-package connector. 
     
     
         15 . The package of  claim 14 , wherein the intermediate inter-package connector comprises a conductive particle and an insulating resin. 
     
     
         16 . The package of  claim 15 , wherein the intermediate inter-package connector further comprises an anisotropic conductive paste. 
     
     
         17 . The package of  claim 14 , wherein the intermediate inter-package connector comprises a middle portion that is narrower than end portions thereof. 
     
     
         18 . The package of  claim 14 , wherein the intermediate inter-package connector comprises a smaller volume than each of the lower inter-package connector and the upper inter-package connector. 
     
     
         19 . A stack package comprising:
 a lower package comprising a lower package substrate, a first lower land disposed on a top surface of the lower package substrate, a second lower land disposed on a bottom surface of the lower package substrate, a lower semiconductor chip disposed on the top surface of the lower package substrate, and a lower molding material surrounding a side surface of the lower semiconductor chip;   an upper package comprising an upper package substrate, a first upper land disposed on a top surface of the upper package substrate, a second upper land disposed on a bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the top surface of the upper package substrate;   an adhesive fastening element disposed between the lower semiconductor chip and the upper package substrate; and   a halogen-free inter-package connector separated from the fastening element and electrically connecting the first lower land to the second upper land,   wherein an air space exists between the lower molding material, the upper package substrate, the fastening element, and the inter-package connector.   
     
     
         20 . A stack package comprising:
 a lower package comprising a lower package substrate and a lower semiconductor chip disposed on the lower package substrate;   an upper package comprising an upper package substrate and an upper semiconductor chip disposed on the upper package substrate;   a fastening element disposed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, wherein the fastening element physically bonds and fixes the lower semiconductor chip to the upper package substrate; and   an inter-package connector to connect a top surface of the lower package substrate to the bottom surface of the upper package substrate, wherein the inter-package connector has an hourglass shape.