Graphene/Nanostructure FET with Self-Aligned Contact and Gate

Abstract

A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

1 . A field effect transistor (FET), comprising:
 a substrate;   a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure;   a gate located on a first portion of the channel material; and   a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.   
     
     
         2 . The FET of  claim 1 , wherein the nanostructure comprises one of carbon nanotubes or semiconductor nanowires. 
     
     
         3 . The FET of  claim 1 , further comprising a spacer comprising one of an oxide or a nitride adjacent to the gate. 
     
     
         4 . The FET of  claim 1 , further comprising a substrate located under the channel material, the substrate comprising an oxide layer over a silicon layer, wherein the channel material is located on the oxide layer. 
     
     
         5 . The FET of  claim 1 , wherein the gate comprises a gate dielectric layer, and a gate metal layer on top of the gate dielectric layer. 
     
     
         6 . The FET of  claim 5 , wherein the gate dielectric layer comprises hafnium oxide (HfO 2 ), the gate metal layer comprises one of titanium nitride (TiN) and tungsten (W), and wherein the gate further comprises a gate hardmask over the gate metal layer, the gate hardmask comprising silicon nitride (SiN).