Method of fabrication of a three-dimensional integrated circuit device using a wafer scale membrane

Abstract

Methods of fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO 2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

1 . A method for fabricating three-dimensional integrated circuits, the method comprising:
 etching crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a device side of the donor semiconductor wafer, to remove at least a substantial portion of the crystalline substrate within the area; and   supporting the donor semiconductor wafer with a supporting structure, the supporting structure allowing flexing of the donor semiconductor wafer within at least a portion of the area after the etching.   
     
     
         2 . The method of  claim 1 , wherein the area comprises an entire side of the substrate side, and wherein the supporting structure comprises a separate supporting structure attached to the donor semiconductor wafer prior to the etching. 
     
     
         3 . The method of  claim 2 , wherein the supporting structure comprises a plurality of additional support partitions that form a grid structure, the grid structure being aligned with edges of die across the donor semiconductor wafer. 
     
     
         4 . The method of  claim 1 , further comprising:
 coating the device side of the donor semiconductor wafer with a first polymer film that is resistant to etching chemistries;   exposing the substrate side to an oxidizing plasma to create a continuous native silicon dioxide film on a surface of the substrate side that is opposite the device side;   defining the area by coating portions of the substrate side outside the area with donor polymer film that is resistant to etching chemistries,   wherein the etching comprises:
 etching the substrate side with a plasma etch tool to substantially thin the crystalline substrate to within a pre-determined thickness; and 
 exposing the substrate side to TMAH to etch silicon portions of the substrate side and not etch silicon dioxide portions of the substrate side, and 
   wherein the supporting structure comprises portions of the substrate side that are outside of the area and that are not etched by the etching.   
     
     
         5 . The method of  claim 4 , wherein the plasma etch tool comprises a clamping ring that protects at least a part of the substrate side that is outside of the area. 
     
     
         6 . The method of  claim 5 , wherein the area comprises a surface of the substrate side that is within an annular ring with a predefined width at the outer edge of the substrate side, and wherein the clamping ring protects the annular ring. 
     
     
         7 . The method of  claim 4 , wherein the area comprises a surface of the substrate side that is within an annular ring having a predefined width at the outer edge of the substrate side. 
     
     
         8 . The method of  claim 7 , wherein the donor semiconductor wafer comprises, adjacent to an inner surface of the crystalline substrate, an insulating layer, and
 wherein the etching removes all of the crystalline substrate within the area so as to expose the insulating layer.   
     
     
         9 . The method of  claim 7 , wherein the etching removes a portion of the crystalline substrate within the area so as to leave a layer of crystalline substrate with a pre-determined thickness. 
     
     
         10 . The method of  claim 7 , wherein the area is further defined to exclude at least one additional support partition within the annular ring. 
     
     
         11 . The method of  claim 10 , wherein the at least one additional support partition comprises a plurality of additional support partitions that form a grid structure, the grid structure being aligned with edges of die across the donor semiconductor wafer. 
     
     
         12 . The method of  claim 1 , further comprising bonding at least a portion of the device side of the donor semiconductor wafer to a device side of an acceptor semiconductor wafer such that the flexing of the donor semiconductor wafer conforms the device side of the donor semiconductor wafer to the device side of the acceptor semiconductor wafer. 
     
     
         13 . The method of  claim 12 , wherein the supporting structure comprises a plurality of additional support partitions that form a grid structure defining a plurality of cavities, the grid structure being aligned with edges of die across the donor semiconductor wafer and each cavity within the plurality of cavities circumscribing at least one die on the donor semiconductor structure,
 the method further comprising positioning, after the etching and the supporting, the device side of the donor semiconductor wafer in proximity to and removed from the device side of the acceptor semiconductor wafer, the positioning causing at least one die on the donor semiconductor wafer to be aligned with a corresponding at least one die on the acceptor wafer, and   wherein the bonding comprises adjusting a pressure within at least one cavity of the plurality of cavities to urge the at least one die circumscribed by at least one cavity into contact with the device side of the acceptor semiconductor wafer.   
     
     
         14 . The method of  claim 12 , further comprising:
 positioning, after the etching and the supporting, the device side of the donor semiconductor wafer in proximity to and removed from the device side of the acceptor semiconductor wafer, the positioning causing the at least one die on the donor semiconductor wafer to be aligned with a corresponding at least one die on the acceptor wafer, and   wherein the bonding comprises adjusting an internal pressure on a backside of the donor semiconductor wafer to urge the device side of the donor semiconductor wafer into contact with the device side of the acceptor semiconductor wafer, wherein the backside is opposite the device side of the donor wafer.   
     
     
         15 . The method of  claim 14 , wherein the etching comprises etching the crystalline substrate so as to allow light to pass through a portion of the donor semiconductor wafer within the area, and
 wherein the positioning comprises optically sensing a position of the acceptor semiconductor wafer relative to the donor semiconductor wafer.