Circuit board

Abstract

A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.

1 . A circuit board, comprising:
 a circuit substrate, having a first surface and at least one first circuit;   a dielectric layer, disposed on the circuit substrate, covering the first surface and the at least one first circuit, and having a second surface, at least one blind via extending from the second surface to the first circuit, a second intaglio pattern, and a third intaglio pattern, wherein the third intaglio pattern is connected to the at least one blind via; and   a patterned circuit structure, comprising:
 at least one second circuit, disposed within the second intaglio pattern; 
 a plurality of third circuits, disposed within the third intaglio pattern and the at least one blind via, each of the plurality of third circuits having a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and the third intaglio pattern and between the second conductive layer and the at least one blind via, wherein a material of the first conductive layer is substantially the same as a material of the at least one second circuit, a line width of the at least one second circuit is thinner than a line width of each of the plurality of third circuits, and at least one of the plurality of third circuits is electrically connected to the at least one first circuit of the circuit substrate. 
   
     
     
         2 . The circuit board as claimed in  claim 1 , wherein the circuit substrate further comprises a first intaglio pattern disposed on the first surface and the at least one first circuit is disposed within the first intaglio pattern. 
     
     
         3 . The circuit board as claimed in  claim 1 , wherein the at least one first circuit is disposed on the first surface of the circuit substrate. 
     
     
         4 . The circuit board as claimed in  claim 1 , wherein a material of the dielectric layer comprises a polymer compound. 
     
     
         5 . The circuit board as claimed in  claim 4 , wherein a material of the polymer compound comprises epoxy, modified epoxy, polyester, acrylate, fluoro-polymer, polyphenylene oxide, polyimide, phenolicresin, polysulfone, silicone polymer, bismaleimide triazine modified epoxy(BT resin), ajinomoto build-up film epoxy(ABF resin), cyanate ester, polyethylene, polycarbonate, acrylonitrile-butadiene-styrene copolymer, polyethylene terephthalate, polybutylene terephthalate, liquid crystal polymers, polyamide 6, nylon, polyoxymethylene, polyphenylene sulfide, cyclic olefin copolymer, or a combination thereof. 
     
     
         6 . The circuit board as claimed in  claim 1 , wherein the second circuit is an electroless copper plating layer. 
     
     
         7 . The circuit board as claimed in  claim 1 , wherein the second circuit is an electroless copper layer. 
     
     
         8 . The circuit board as claimed in  claim 1 , wherein the first conductive layer is an electroless copper plating layer. 
     
     
         9 . The circuit board as claimed in  claim 1 , wherein the first conductive layer is an electroless copper layer. 
     
     
         10 . The circuit board as claimed in  claim 1 , wherein the second conductive layer is an electroplated copper layer.