Test apparatus for digital modulated signal

Abstract

A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.

1 - 12 . (canceled) 
     
     
         13 . A digital modulator comprising:
 a first baseband signal generator configured to perform, using a first timing signal the timing of which can be adjusted, retiming of first data input as a modulation signal for an in-phase component so as to generate a first baseband signal;   a second baseband signal generator configured to perform, using a second timing signal the timing of which can be adjusted, retiming of second data input as a modulation signal for a quadrature component so as to generate a second baseband signal;   a first multi-level driver configured to generate a first multi-value digital signal having a level that corresponds to the value of the baseband signal output from the first baseband signal generator;   a second multi-level driver configured to generate a second multi-value digital signal having a level that corresponds to the value of the baseband signal output from the second baseband signal generator;   a first multiplier configured to amplitude-modulate an in-phase carrier signal with the first multi-value digital signal;   a second multiplier configured to amplitude-modulate a quadrature carrier signal with the second multi-value digital signal; and   an adder configured to sum the output signals of the first and second multipliers.   
     
     
         14 . A digital modulator according to  claim 13 , wherein the in-phase carrier signal and the quadrature carrier signal are each generated in the form of a rectangular pulse signal. 
     
     
         15 . A semiconductor apparatus comprising:
 a function device having a plurality of input/output ports; and   a plurality of digital modulators according to  claim 13 , configured to digitally modulate the data output via the input/output ports of the function device, and to output the data thus digitally modulated to an external circuit.   
     
     
         16 . A test apparatus configured to receive data subjected to digital multi-value modulation, from a device under test configured to transmit and receive multi-channel data subjected to digital multi-value modulation, the test apparatus comprising digital demodulators in increments of channels,
 wherein the digital demodulator comprises:
 a third multiplier configured to perform down-conversion of the data thus received using an in-phase detection signal; 
 a fourth multiplier configured to perform down-conversion of the data thus received using a quadrature detection signal; 
 a first comparator configured to compare a third multi-value digital signal output from the third multiplier with at least one predetermined threshold voltage; 
 a second comparator configured to compare a fourth multi-value digital signal output from the fourth multiplier with at least one predetermined threshold voltage; 
 a first latch circuit configured to latch a third digital baseband signal output from the first comparator using a third timing signal, the timing of which can be adjusted; and 
 a second latch circuit configured to latch a fourth digital baseband signal output from the second comparator using a fourth timing signal, the timing of which can be adjusted, 
   and wherein the data thus latched by the first and second latches are compared with expected value data.   
     
     
         17 . A test apparatus according to  claim 16 , wherein the first and second comparators are each configured such that the threshold voltages thereof can be adjusted. 
     
     
         18 . A test apparatus according to  claim 17 , wherein the threshold voltage of the first comparator and the threshold voltage of the second comparator can be independently adjusted. 
     
     
         19 . A test apparatus according to  claim 16 , wherein the third and fourth multipliers are each configured such that the gains thereof can be independently adjusted. 
     
     
         20 . A test apparatus according to  claim 16 , further comprising:
 an oscillator configured to generate a detection signal having a carrier frequency; and   a phase shifter configured to shift the phase of the detection signal generated by the oscillator, and to generate the in-phase detection signal and the quadrature detection signal.   
     
     
         21 . A test apparatus according to  claim 20 , wherein the phase shifter is configured to be capable of adjusting the phase difference between the in-phase detection signal and the quadrature detection signal. 
     
     
         22 . A test apparatus according to  claim 16 , wherein the in-phase detection signal and the quadrature detection signal are each generated in the form of a rectangular pulse signal. 
     
     
         23 . A test apparatus according to  claim 16 , further comprising:
 a direct digital synthesizer configured to digitally generate a user-desired signal waveform; and   a digital/analog converter configured to perform digital/analog conversion of the output data output from the direct digital synthesizer, and to generate the in-phase detection signal and the quadrature detection signal.   
     
     
         24 . A test apparatus according to  claim 16 , further comprising a timing generator configured to generate a pulse signal having a frequency and a level transition timing which can be adjusted,
 wherein the in-phase detection signal and the quadrature detection signal are generated by means of the timing generator.   
     
     
         25 . A digital demodulator comprising:
 a third multiplier configured to perform down-conversion of received data using an in-phase detection signal;   a fourth multiplier configured to perform down-conversion of received data using a quadrature detection signal;   a first comparator configured to compare a third multi-value digital signal output from the third multiplier with at least one predetermined threshold voltage;   a second comparator configured to compare a fourth multi-value digital signal output from the fourth multiplier with at least one predetermined threshold voltage;   a first latch circuit configured to latch a third digital baseband signal output from the first comparator using a third timing signal having a timing which can be adjusted; and   a second latch circuit configured to latch a fourth digital baseband signal output from the second comparator using a fourth timing signal having a timing which can be adjusted.   
     
     
         26 . A digital demodulator according to  claim 25 , wherein the in-phase detection signal and the quadrature detection signal are each generated in the form of a rectangular pulse signal. 
     
     
         27 . A semiconductor apparatus comprising:
 a function device having a plurality of input/output ports; and   a plurality of digital de modulators according to  claim 25 , configured to demodulate data input from an external circuit, and to output the data thus demodulated to the corresponding port of the function device.