Structure and method for single gate non-volatile memory device

Abstract

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a periphery region and a memory region; a field effect transistor disposed in the periphery region and having silicide features; and a single floating gate non-volatile memory device disposed in the memory region, free of silicide and having a first gate electrode and a second gate electrode laterally spaced from each other.

1 . An integrated circuit, comprising:
 a semiconductor substrate having a periphery region and a memory region;   a field effect transistor disposed in the periphery region and having silicide features; and   a single floating gate non-volatile memory device disposed in the memory region, free of silicide and having a first gate electrode and a second gate electrode laterally spaced from each other.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the single floating gate non-volatile memory device in the memory region includes a first region and a second region approximate the first region, wherein
 the first region includes a first structure and the second region includes a second structure;   the first structure is designed operable to store charges and includes:
 a first gate dielectric feature over the semiconductor substrate; 
 the first gate electrode disposed on the first gate dielectric feature and configured to be floating; and 
 source and drain formed in the semiconductor substrate, disposed on both sides of the first gate electrode; and 
   the second structure is coupled with the first structure for data operations, and includes:
 a second gate dielectric feature over the semiconductor substrate; and 
 the second gate electrode disposed on the second gate dielectric feature. 
   
     
     
         3 . The integrated circuit of  claim 2 , wherein the first structure is configured as a transistor with a floating gate coupled with the second gate electrode and the second structure is configured as a capacitor. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the second structure further includes:
 a doped well of a first type dopant formed in the semiconductor substrate and underlying the second gate electrode; and   a doped contact of the first type dopant formed in the semiconductor substrate and contacting the doped well,   wherein the capacitor includes the doped well as a first capacitor electrode, the second gate electrode as a second capacitor electrode, and the second gate dielectric feature as a capacitor dielectric sandwiched between the first and second capacitor electrodes.   
     
     
         5 . The integrated circuit of  claim 3 , wherein the second structure further includes:
 a doped well of a first type dopant formed in the semiconductor substrate and underlying the second gate electrode; and   a doped contact of a second type dopant formed in the semiconductor substrate and contacting the doped well, the second type dopant being opposite to the first type dopant,   wherein the capacitor includes the doped well as a first capacitor electrode, the second gate electrode as a second capacitor electrode, and the second gate dielectric feature as a capacitor dielectric sandwiched between the first and second capacitor electrodes.   
     
     
         6 . The integrated circuit of  claim 2 , wherein
 the first structure is configured as a floating gate transistor and the second structure is configured as a select transistor serially connected with the floating gate transistor; and   the select transistor and the floating gate transistor share the drain.   
     
     
         7 . The integrated circuit of  claim 2 , wherein
 the first structure is configured as a floating gate transistor and the second structure is configured as an injection transistor;   the injection transistor and the floating gate transistor share the drain; and   the second gate electrode is electrically connected with the first gate electrode.   
     
     
         8 . The integrated circuit of  claim 7 , wherein
 the source of the floating gate transistor is coupled to a read bit line;   the drain is coupled to a word line; and   a source of the injection transistor is coupled to an injection bit line.   
     
     
         9 . The integrated circuit of  claim 2 , wherein the field effect transistor in the periphery region includes:
 a third gate disposed on a third gate dielectric feature;   a source and a drain formed in the semiconductor substrate and interposed by the third gate; and   the silicide features formed on the source, drain, and the third gate of the field effect transistor in the periphery region, and being further coupled to an interconnect structure for respective electrical bias.   
     
     
         10 . The integrated circuit of  claim 2 , wherein the second gate is electrically connected to the first gate and is electrically floating. 
     
     
         11 . An integrated circuit, comprising:
 a semiconductor substrate having a periphery region and a memory region, wherein the periphery region includes silicide features disposed on various contact areas and the memory region is free of silicide; and   a plurality of single floating gate non-volatile memory cells disposed in the memory region, wherein each of the single floating gate non-volatile memory cells includes:
 a first gate electrode disposed on the semiconductor substrate, separated by a first gate dielectric feature from the semiconductor substrate and configured to be floating for storing charges; 
 a source and a drain formed in the semiconductor substrate, respectively disposed on both sides of the first gate; and 
 a second gate electrode disposed on the semiconductor substrate, separated by a second gate dielectric feature from the semiconductor substrate and laterally distanced from the first gate electrode. 
   
     
     
         12 . The integrated circuit of  claim 11 , wherein the second gate electrode is electrically connected with an interconnect structure for electrical bias. 
     
     
         13 . The integrated circuit of  claim 11 , further comprising a source in the semiconductor substrate and disposed at an edge of the second gate electrode, wherein the second gate electrode is electrically connected with the first gate electrode and the source at the edge of the second gate electrode is configured operable to charge the first gate electrode. 
     
     
         14 . The integrated circuit of  claim 11 , further comprising
 a first doped region of a first type dopant in the semiconductor substrate and directly underlying the second gate electrode; and   a second doped region of the first type dopant in the semiconductor substrate and contacting the first doped region,   wherein the second gate electrode is electrically connected with the first gate electrode, and the second doped region is configured operable to charge the first gate electrode.   
     
     
         15 . The integrated circuit of  claim 11 , wherein
 the single floating gate memory device in the memory region includes a first region and a second region approximate the first region;   the first region includes the first gate dielectric feature, the first gate electrode, the source and the drain configured as a transistor;   the second region includes a doped well in the semiconductor substrate and directly underlying the second gate dielectric feature, the second gate dielectric feature, and the second gate electrode configured as a capacitor; and   the second gate electrode is electrically connected with the first gate electrode.   
     
     
         16 . The integrated circuit of  claim 15 , further comprising a shallow trench isolation (STI) in the semiconductor substrate and disposed between the drain of the transistor and the doped well. 
     
     
         17 . The integrated circuit of  claim 11 , further comprising
 a hard mask layer of a first dielectric material on the semiconductor substrate within the memory region;   an etch stop layer of a second dielectric material on the semiconductor substrate and partially on the hard mask layer;   an inter-level dielectric (ILD) layer of a third dielectric material on the etch stop layer;   a first plurality of contact features in the memory region and embedded in the hard mask layer, the etch stop layer, and the ILD layer; and   a second plurality of contact features in the periphery region, embedded in the hard mask layer, the etch stop layer and the ILD layer and contacting the silicide features,   wherein the second dielectric material is different from the first dielectric material and the third dielectric material.   
     
     
         18 . A method of making an integrated circuit, the method comprising:
 providing a silicon substrate having a memory region and a periphery region;   forming a gate dielectric layer on the silicon substrate and a gate electrode layer on the gate dielectric layer;   patterning the gate electrode layer and the gate dielectric layer, resulting in a first gate stack and a second gate stack in the memory region and a third gate stack in the periphery region, the second gate stack being laterally distanced from the first gate stack;   performing various implantations to the silicon substrate, forming a first source and a first drain on both sides of the first gate stack and a second source and a second drain on both sides of the third gate stack;   forming a hard mask layer on the silicon substrate, wherein the hard mask layer covers the memory region and exposes the third gate stack, the second source and the second drain in the periphery region; and   forming silicide on the third gate stack, the second source and the second drain in the periphery region while the memory region is protected from forming silicide by the hard mask layer.   
     
     
         19 . The method of  claim 18 , wherein forming silicide includes:
 depositing a metal layer on the silicon substrate through the hard mask layer;   performing an annealing process to the silicon substrate to react the metal layer with the silicon substrate; and   etching to remove un-reacted portion of the metal layer.   
     
     
         20 . The method of  claim 18 , after forming silicide, further comprising:
 forming an inter-level dielectric (ILD) layer on the silicon substrate;   etching the ILD layer to form contact holes, respectively aligned with the first source and first drain in the memory region and the second source and the second drain in the periphery region;   etching the hard mask layer within the contact holes of the memory region; and   forming conductive plugs in the contact holes.   
     
     
         21 . The method of  claim 20 , wherein etching the hard mask layer includes implementing an etching process tuned to selectively etch the hard mask layer without significant damage to the silicide within the contact holes of the periphery region. 
     
     
         22 . The method of  claim 20 , before forming conductive plugs, further comprising
 forming an etch stop layer on the silicon substrate before forming an ILD layer such that the etch stop layer is overlying the hard mask layer and the silicide and is underlying the ILD layer;   etching the etch stop layer after etching the ILD layer; and   thereafter etching the hard mask layer.   
     
     
         23 . The method of  claim 20 , before forming conductive plugs, further comprising
 forming an etch stop layer on the silicon substrate before forming an ILD layer such that the etch stop layer is overlying the hard mask layer and the silicide and is underlying the ILD layer; and   performing an etching process to the etch stop layer and the hard mask layer after etching the ILD layer, wherein the etching process is tuned to substantially remove the etch stop layer and the hard mask layer without damage to the silicide features.