Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells

Abstract

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

What is claimed is: 
     
         1 . A memory cell, comprising:
 a first electrode;   a second electrode;   a discrete two-terminal re-writeable non-volatile memory element including
 a plurality of layers of conductive metal oxide (CMO) that are in contact with one another and including
 a first layer of CMO in contact with the first electrode and including mobile oxygen ions, 
 a second layer of CMO in contact with the first layer of CMO and configured to cooperate with the first layer of CMO to form an ion obstruction barrier positioned in a portion of both the first and second CMO layers and operative to inhibit transport of other mobile ions when a voltage for data operations is not being applied across the first electrode and the second electrode, and 
 
 a layer of insulating metal oxide (IMO) formed in contact with the second layer of CMO, the layer of IMO being permeable to the mobile oxygen ions when a write voltage is applied across the first and second electrodes, 
 wherein the second layer of CMO has a second thickness that is less than a first thickness of the first layer of CMO. 
   
     
     
         2 . The memory cell of  claim 1 , wherein the first layer of CMO and the second layer of CMO have different compositions. 
     
     
         3 . The memory cell of  claim 2 , wherein the first layer of CMO is formed with a grain size and a grain orientation, and the grain size and the grain orientation are replicated in the second layer of CMO. 
     
     
         4 . The memory cell of  claim 2 , wherein the different compositions of the first layer of CMO and the second layer of CMO include different elements. 
     
     
         5 . The memory cell of  claim 2 , wherein the different compositions of the first layer of CMO and the second layer of CMO include identical elements and different stoichiometries. 
     
     
         6 . The memory cell of  claim 2 , wherein the different compositions of the first layer of CMO and the second layer of CMO include identical elements and identical stoichiometries with different concentrations of oxygen ions. 
     
     
         7 . The memory cell of  claim 1 , wherein the first layer of CMO, the second layer of CMO, or both are formed in whole or in part using atomic layer deposition (ALD). 
     
     
         8 . The memory cell of  claim 7 , wherein the portion of both the first and second layers of CMO comprises an ion-implanted material operative to form the ion obstruction barrier. 
     
     
         9 . The memory cell of  claim 1 , wherein the first layer of CMO is formed to have a thickness from about 50 to about 250 Angstroms, and the second layer of CMO is formed to have a thickness from about 5 to about 25 Angstroms. 
     
     
         10 . The memory cell of  claim 9 , wherein the second layer of CMO is formed to have a thickness from about 10 to about 20 Angstroms. 
     
     
         11 . The memory cell of  claim 9 , wherein the ion obstruction barrier is configured to provide a ratio of on-current to off-current for the memory element that is equal to or greater than 10 2 . 
     
     
         12 . The memory cell of  claim 1 , wherein the ion obstruction barrier is configured to provide a cycling endurance for the memory element ranging from about 100,000 to about 1,000,000 program-erase cycles, or greater. 
     
     
         13 . The memory cell of  claim 1 , wherein the first layer of CMO and the second layer of CMO reside in planes at an acute angle with a surface of a substrate. 
     
     
         14 . The memory cell of  claim 1 , wherein the layer of IMO is formed in whole or in part using atomic layer deposition (ALD). 
     
     
         15 . The memory cell of  claim 1 , wherein the layer of IMO has a thickness that is approximately 50 Angstroms or less. 
     
     
         16 . The memory cell of  claim 1 , wherein the discrete two-terminal re-writeable non-volatile memory element includes a non-linear I-V characteristic that is independent of a value of non-volatile data stored in the memory element. 
     
     
         17 . The memory cell of  claim 1 , wherein the discrete two-terminal re-writeable non-volatile memory element stores at least one-bit of non-volatile data that is retained in the absence of electrical power. 
     
     
         18 . An integrated circuit, comprising:
 a substrate;   a logic layer including active circuitry fabricated front-end-of-the-line (FEOL) on the substrate; and   a two-terminal cross point memory array fabricated back-end-of-the-line (BEOL) directly above and in direct contact with the substrate, the two-terminal cross point memory array including
 X-line conductive array lines, 
 Y-line conductive array lines arranged orthogonal to the X-line conductive array lines, the X-line and Y-line conductive array lines electrically coupled with at least a portion of the active circuitry, and 
 discrete memory elements, each memory element disposed between a cross-point of one of the X-line conductive array lines with one of the Y-line conductive array lines, 
 each memory element including
 a first electrode in contact with a first portion of the memory element and a second electrode in contact with a second portion of the memory element; 
 a layer of insulating metal oxide (IMO), 
 a dual-layered conductive metal oxide (CMO) including
 a first layer of CMO formed in the first portion of the memory element and including mobile oxygen ions, 
 a second layer of CMO formed upon the first layer of CMO, whereby crystalline orientations and sizes of grains in the first layer of CMO are replicated in the second layer of CMO, and 
 an active region positioned in the first layer of CMO and the second layer of CMO and operative to impede diffusion of positively-charged ions between the IMO and the first layer of the CMO. 
 
 
   
     
     
         19 . The integrated circuit of  claim 18 , wherein the active region comprises an ion-implanted material including argon elements. 
     
     
         20 . The integrated circuit of  claim 18 , wherein the first layer of CMO and the second layer of CMO comprise different compositions based on one or more of the following selected from the group consisting of different elements, different stoichiometries, and different concentrations of oxygen ions. 
     
     
         21 . The integrated circuit of  claim 18 , wherein the second layer of CMO is formed to have a thickness between about 10% and about 20% of the thickness of the first layer of CMO. 
     
     
         22 . The integrated circuit of  claim 18 , wherein each memory element includes a non-linear I-V characteristic that is independent of a value of non-volatile data stored in the memory element. 
     
     
         23 . The integrated circuit of  claim 18 , wherein a selected one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO are deposited in whole or in part using atomic layer deposition (ALD). 
     
     
         24 . A method of forming two-terminal non-volatile re-writeable resistive memory elements, comprising:
 depositing an electrode;   forming a first layer of conductive metal oxide (CMO) on a first surface of the electrode, the first layer of CMO being a reservoir for mobile oxygen ions;   forming a second layer of CMO having similarly-dimensioned crystalline structures as the first layer of CMO on a second surface of the first layer of CMO; and   ion implanting an element at a depth through the second layer of CMO to reach a portion of the first layer of CMO to form an ion obstruction barrier configured to inhibit transport of other mobile ions between the first layer of CMO and a layer of insulating metal oxide (IMO).   
     
     
         25 . The method of  claim 24 , wherein forming the second layer of CMO comprises forming the second layer of CMO at a thickness from about 10 Angstroms to about 20 Angstroms. 
     
     
         26 . The method of  claim 24 , wherein the other mobile ions comprise metal cations. 
     
     
         27 . The method of  claim 24  and further comprising: forming a layer of IMO on a third surface of the second layer of CMO. 
     
     
         28 . The method of  claim 27 , wherein a selected one or more of the layer of IMO, the first layer of CMO, or the second layer of CMO are formed in whole or in part using atomic layer deposition (ALD). 
     
     
         29 . The method of  claim 24 , wherein the electrode is formed on a substantially planar upper surface of an electrically conductive support layer.