Packaging Structures of Integrated Circuits

Abstract

A chip includes a dummy connector disposed at a top surface of the chip. A seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector.

1 . A device comprising:
 a first chip comprising:
 a dummy connector disposed at a top surface of the first chip, wherein the dummy connector is not adjacent to at least one of edges of the first chip; and 
 a seal ring encircling a region directly underlying the dummy connector, with the region overlapping the dummy connector; and 
   a second chip comprising a connector disposed at a top surface of the second chip, wherein the second chip is connected to the first chip and the connector is connected to the dummy connector.   
     
     
         2 . The device of  claim 1 , wherein in a top view of the first chip, the seal ring does not encircle any active electrical connector in the first chip. 
     
     
         3 . The device of  claim 1 , wherein the first chip further comprises:
 a plurality of dummy connectors disposed at the top surface of the first chip; and   a plurality of seal rings, wherein in a top view of the first chip, each of the seal rings encircles one of the plurality of dummy connectors, and wherein each of the plurality of seal rings is separated from each other.   
     
     
         4 . The device of  claim 1  further comprising an additional seal ring disposed in a peripheral region of the first chip and adjacent to edges of the first chip, and wherein the seal ring and the additional seal ring extend into same layers of the first chip. 
     
     
         5 . The device of  claim 4 , wherein the seal ring is disposed in a region encircled by the additional seal ring. 
     
     
         6 . The device of  claim 4 , wherein the seal ring and the additional seal ring are interconnected, and share a common portion. 
     
     
         7 . The device of  claim 1 , wherein the seal ring extends into a plurality of metal layers comprising a bottom metal layer of the first chip and a top metal layer of the first chip, and wherein the seal ring comprises a metal line forming a ring in each of the plurality of metal layers, and vias interconnecting metal lines in the plurality of metal layers. 
     
     
         8 . A device comprising:
 a first chip comprising:
 a first seal ring disposed in peripheral regions of the first chip, wherein the peripheral regions are adjacent to edges of the first chip; 
 a plurality of dummy connectors disposed at a top surface of the first chip and adjacent to the first seal ring; 
 a plurality of active electrical connectors, wherein the plurality of active electrical connectors are formed of a same material, and at a same level, as the plurality of dummy connectors; and 
 a plurality of second seal rings, wherein each of the plurality of second seal rings encircles a region directly underlying one of the plurality of dummy connectors, and wherein each of the plurality of second seal rings is separated from each other, and is separated from the first seal ring; and 
   a second chip comprising a plurality of connectors disposed at the top surface of the second chip, wherein the second chip is connected to the first chip and the plurality of connectors is connected to the plurality of dummy connectors.   
     
     
         9 . The device of  claim 8 , wherein none of the plurality of active electrical connectors is encircled by the plurality of second seal rings. 
     
     
         10 . The device of  claim 8 , wherein in a top view of the first chip, each of the plurality of second seal rings encircles a single dummy connector, and wherein the each of the plurality of second seal rings does not encircle any one of the plurality of active electrical connectors. 
     
     
         11 . The device of  claim 8 , wherein the plurality of second seal rings is disposed adjacent to corner regions of the first chip, and is not adjacent to at least one of edges of the first chip. 
     
     
         12 . The device of  claim 8 , wherein each of the plurality of second seal rings encircles a single one of the plurality of dummy connectors in a top view of the first chip. 
     
     
         13 . The device of  claim 8 , wherein the plurality of dummy connectors, the plurality of active electrical connectors, and the plurality of second seal rings are encircled by the first seal ring in a top view of the first chip. 
     
     
         14 . The device of  claim 8 , wherein the plurality of second seal rings and the first seal ring extend into same metal layers of the first chip. 
     
     
         15 . A device comprising:
 a first chip comprising:
 a first seal ring disposed in peripheral regions of the first chip, wherein the peripheral regions are adjacent to edges of the first chip; 
 a dummy connector disposed at a top surface of the first chip and adjacent to a corner of the first chip; and 
 a second seal ring encircling a region directly under the dummy connector, wherein the second seal ring and the first seal ring share a common portion; and 
   a second chip comprising a connector disposed at a top surface of the second chip, wherein the second chip is connected to the first chip and the connector is connected to the dummy connector.   
     
     
         16 . The device of  claim 15  further comprising a plurality of active electrical connectors at the top surface of the first chip, wherein the plurality of active electrical connectors is not encircled by any of second seal ring in the first chip. 
     
     
         17 . The device of  claim 15 , wherein the second seal ring further comprises a portion not shared with the first seal ring, and wherein the portion not shared with the first seal ring is disposed inside the first seal ring. 
     
     
         18 . The device of  claim 15 , wherein all dummy connectors in the first chip are encircled by additional seal rings in the chip, and wherein none of active electrical connectors in the first chip is encircled by any of the additional seal rings in the first chip. 
     
     
         19 . The device of  claim 15 , wherein the second seal ring and the first seal ring extend into a same plurality of metal layers of the first chip, and wherein the second seal ring comprises a metal line forming a ring in each of the plurality of metal layers, and vias interconnecting metal lines in the plurality of metal layers. 
     
     
         20 . The device of  claim 15 , wherein the second seal ring shares a corner part of the first seal ring with the first seal ring.