High Voltage Device and Manufacturing Method Thereof

Abstract

The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.

What is claimed is: 
     
         1 . A high voltage device, which is formed in a substrate, wherein the substrate has an upper surface, the high voltage device comprising:
 a gate, which is formed on the upper surface of the substrate;   a source and a drain, which are located at both sides of the gate below the upper surface respectively, and are separated by the gate from cross-section view;   a drift region, which has a same conduction type with the drain, and is located at least between the gate and the drain; and   a mitigation region, which has a same conduction type with the drain, and is formed below the drift region from cross-section view,   wherein the drift region has an edge closer to the source, and a vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.   
     
     
         2 . The high voltage device of  claim 1 , wherein the mitigation region does not overlap the source from top view. 
     
     
         3 . The high voltage device of  claim 1 , wherein the high voltage device is an N-type double diffused drain metal oxide semiconductor (NDDMOS) device. 
     
     
         4 . The high voltage device of  claim 1 , wherein the substrate further includes an epitaxial layer, and the mitigation layer is formed below the epitaxial layer. 
     
     
         5 . A manufacturing method of a high voltage device, comprising:
 providing a substrate, wherein the substrate has an upper surface;   forming a drift region below the upper surface, and forming a mitigation region below the drift region;   forming a gate on the upper surface of the substrate; and   forming a source and a drain at both sides of the gate below the upper surface respectively, which are separated by the gate from cross-section view, wherein the drain and the gate are separated by the drift region;   wherein the drift region, the mitigation region, the source and the drain have a same conductive type, and the drift region has an edge closer to the source, wherein a vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.   
     
     
         6 . The manufacturing method of  claim 5 , wherein the mitigation region does not overlap the source from top view. 
     
     
         7 . The manufacturing method of  claim 5 , wherein the high voltage device is an N-type double diffused drain metal oxide semiconductor (NDDMOS) device. 
     
     
         8 . The manufacturing method of  claim 5 , wherein the substrate further includes an epitaxial layer, and the mitigation layer is formed below the epitaxial layer.