Semiconductor package featuring flip-chip die sandwiched between metal layers

Abstract

Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices.

What is claimed is: 
     
         1 . A package for a semiconductor device, the package comprising:
 a first metal layer configured to be in thermal and electrical communication with a power device die; and   a second metal layer disposed on an opposite side of the power device die from the first metal layer, the second metal layer configured to be in electrical and thermal communication with a pad on a surface of the power device die through physical contact with a solder ball contact, the first metal layer comprising integral leads projecting from a plastic package body encapsulating the power device die, the solder ball contact, and at least a part of the first and second metal layers;   wherein the first metal layer is configured to be in electrical communication with the power device die through a second solder ball contact.   
     
     
         2 . A package for a semiconductor device, the package comprising:
 a first metal layer configured to be in thermal and electrical communication with a MOSFET die;   a second metal layer disposed on an opposite side of the MOSFET die from the first metal layer, the second metal layer comprising:
 a first portion configured to be in electrical communication with a gate pad on a surface of the MOSFET die, and 
 a second portion configured to be in electrical and thermal communication with a source pad on the surface of the MOSFET die through physical contact with a solder ball contact; and 
   a plastic package body encapsulating the MOSFET die, the solder ball contact, and at least a part of the first and second metal layers, wherein the first metal layer comprises integral leads projecting from the plastic package body.   
     
     
         3 . The package of  claim 2  wherein the first metal layer is configured to be in thermal and electrical communication with a drain on a second surface of the MOSFET die. 
     
     
         4 . The package of  claim 2  comprising at least one additional lead integral with the second metal layer. 
     
     
         5 . A package for a semiconductor device, the package comprising:
 a first metal layer configured to be in at least thermal communication with a first side of a first power device die through physical contact with a first solder ball contact;   a second power device die located above or below the first power device die and in electrical contact with a second side of the first power device die through physical contact with a second solder ball contact; and   a second metal layer disposed on an opposite side of the second power device die from the first power device die, the second metal layer configured to be in at least thermal communication with the second power device die, the first metal layer or the second metal layer comprising integral leads projecting from a plastic package body encapsulating the first power device die, the first solder ball contact, the second solder ball contact, and at least a part of the first and second metal layers, wherein the first power device die or the second power device die is in electrical communication with the first metal layer or the second metal layer.   
     
     
         6 . A method of packaging a semiconductor device, the method comprising:
 providing a first metal layer, wherein:
 the first metal layer is configured to be in thermal and electrical communication with a first surface of a first power device die wherein the first metal layer is provided with a portion bent out of a plane of the first metal layer to form a lead exposed by a package body; and 
 the first metal layer includes a first portion of the first metal layer is configured to be in at least thermal communication with a first surface of a second power device die; 
   providing a second metal layer, wherein:
 the second metal layer is configured to be in thermal and electrical communication with a second surface of the first power device die opposite the first side, through physical contact with a first solder ball contact; and 
 the second metal layer includes a second portion configured to be in electrical and thermal communication with at least one pad on a second surface of the second power device die opposite the first surface, through at least one additional solder ball contact; and 
   encapsulating the first power device die, the second power device die, the first solder ball contact, the at least one additional solder ball contact and at least a part of the first and second metal layers within a plastic encapsulant to form the package body.   
     
     
         7 . The method of  claim 6  wherein the second portion is also in electrical communication with a pad on the second surface of the first power device die. 
     
     
         8 . The method of  claim 6  wherein the first power device die comprises a MOSFET die, and the second portion is in electrical communication with a gate of the MOSFET die. 
     
     
         9 . The method of  claim 6  further comprising providing a third power device die disposed above or below the second power device die and in electrical communication with the second power device die through a second solder ball contact.