Semiconductor device

Abstract

A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2 a, 2 b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10 d and first additional wiring layer for ground 10 s formed on respective additional substrates 2 a, 2 b form prescribed conductive areas on semiconductor chip 1 . First power source wiring 40 C 1d or first ground wiring 40 C 1s are interconnected through additional wiring layers 10 d and 10 s . Second power source wiring 40 C 2d and second ground wiring 40 C 2s , which is extended in the same direction as with DQ system signal wiring 40 C DQ , forms a feedback current path. Second power source wiring 40 C 2d and second ground wiring 40 C 2s are disposed adjacent to DQ system signal wiring 40 C DQ .

What is claimed is: 
     
         1 . A device comprising:
 a substrate including first and second power supply terminals supplied with first and second power supply voltages, respectively;   a semiconductor chip mounted on the substrate and including first and second side edges that cross to each other, first and second power supply pads that are arranged in line along the first side edge; and   a first additional conductive layer formed over the semiconductor chip;   the first additional conductive layer being configured to receive the first power supply voltage beyond the second side edge of the semiconductor chip from the first power supply terminal, the first power supply pad of the semiconductor chip being configured to receive the first power supply voltage from the first additional conductive layer, and the second power supply pad of the semiconductor chip being configured to receive the second power supply voltage beyond the first side edge of the semiconductor chip from the second power supply terminal.   
     
     
         2 . The device as claimed in  claim 1 , wherein the semiconductor chip includes a first circuit configured to operate on the first power supply voltage and a second circuit configured to operate on the second power supply voltage. 
     
     
         3 . The device as claimed in  claim 1 , wherein the substrate includes a first area running along the first side edge of the semiconductor chip and a second area running along the second side edge of the semiconductor chip, the first power supply terminal of the substrate is disposed in the second area of the substrate, and the second power supply terminal of the substrate is disposed in the first area of the substrate. 
     
     
         4 . The device as claimed in  claim 3 , wherein the second area is smaller in length along a direction, in which the second side edge of the semiconductor chip extends, than the second side edge. 
     
     
         5 . The device as claimed in  claim 1 , further comprising:
 a first power supply path connecting the first power supply terminal of the substrate to the first additional conductive layer and including a first bonding wiring that is elongated across the second side edge of the semiconductor chip, and   a second power supply path connecting the second power supply terminal of the substrate to the second power supply pad of the semiconductor chip and including a second bonding wiring that is elongated across the first side edge of the semiconductor chip.   
     
     
         6 . The device as claimed in  claim 1 , wherein the substrate includes a signal terminal, the semiconductor chip includes a signal pad that is arranged in line with the first and second power supply pads along the first side edge of the semiconductor chip, the signal pad of the semiconductor chip is configured to receive an input signal beyond the first side edge of the semiconductor chip from the signal terminal of the substrate. 
     
     
         7 . The device as claimed in  claim 6 , wherein the signal pad of the semiconductor chip is configured to supply an output signal to the signal terminal of the substrate beyond the first side edge of the semiconductor chip. 
     
     
         8 . The device as claimed in  claim 6 , wherein the semiconductor chip includes a first circuit configured to operate on the first power supply voltage and a second circuit configured to operate on the second power supply voltage and the second circuit is coupled to the signal pad of the semiconductor chip to receive the input signal. 
     
     
         9 . The device as claimed in  claim 1 , wherein the substrate includes third and fourth power supply terminals supplied with third and fourth power supply voltages, respectively, the semiconductor chip includes a third side edge opposite to the second side edge and third and fourth power supply pads that are arranged in line with the first and second power supply pads along the first side edge, the device further comprises a second additional conductive layer formed over the semiconductor chip and insulated from the first additional conductive layer, and wherein the second additional conductive layer is configured to receive the third power supply voltage beyond the third side edge of the semiconductor chip from the third power supply terminal, the third power supply pad of the semiconductor chip is configured to receive the third power supply voltage from the second additional conductive layer, and the fourth power supply pad of the semiconductor chip is configured to receive the fourth power supply voltage beyond the first side edge of the semiconductor chip from the fourth power supply terminal to the fourth power supply pad. 
     
     
         10 . A device comprising:
 a semiconductor chip including a first side edge elongated in a first direction, a second side edge elongated in a second direction that is substantially perpendicular to the first direction, and first and second power supply pads that are arranged in line in the first direction;   a substrate including a first area on which the semiconductor chip is mounted and second and third areas, the first and second areas being arranged in line in the first direction, the first and third areas being arranged in line in the second direction, the substrate further including a first power supply terminal disposed in the second area and a second power supply terminal disposed in the third area, the first and the second power supply terminals being configured to be supplied respectively with first and second power supply voltages;   an additional conductive layer formed over the semiconductor chip;   a first power supply path connecting the first power supply terminal of the substrate to the additional conductive layer to convey the first power supply voltage to the additional conductive layer;   a second power supply path connecting the additional conductive layer to the first power supply pad of the semiconductor chip to convey the first power supply voltage to the first power supply pad; and   a third power supply path connecting the second power supply terminal of the substrate to the second power supply pad of the semiconductor chip to convey the second power supply voltage to the second power supply pad.   
     
     
         11 . The device as claimed in  claim 10 , wherein the semiconductor chip includes a first circuit configured to operate on the first power supply voltage and a second circuit configured to operate on the second power supply voltage. 
     
     
         12 . The device as claimed in  claim 10 , wherein the first power supply path includes a first bonding wiring elongated across the second side edges of the semiconductor chip, and the third power supply path includes a second bonding wiring elongated across the first side edges of the semiconductor chip. 
     
     
         13 . The device as claimed in  claim 10 , wherein the semiconductor chip includes a signal pad arranged in line in the first direction with the first and the second power supply pads, and the substrate includes a signal terminal disposed in the third area and supplied with an input signal, and the device further comprises a signal path connecting the signal terminal of the substrate to the signal pad of the semiconductor chip to convey the input signal to the signal pad. 
     
     
         14 . The device as claimed in  claim 13 , wherein the semiconductor chip includes a first circuit configured to operate on the first power supply voltage and a second circuit configured to operate on the second power supply voltage and the second circuit is coupled to the signal pad of the semiconductor chip to receive the input signal. 
     
     
         15 . The device as claimed in  claim 13 , wherein the first power supply path includes a first bonding wiring elongated across the second side edges of the semiconductor chip, the third power supply path includes a second bonding wiring elongated across the first side edges of the semiconductor chip, and the signal path includes a third bonding wiring elongated across the first side edge of the semiconductor substrate. 
     
     
         16 . A device comprising;
 a substrate including a first terminal configured to be supplied with a first power supply voltage;   a semiconductor chip mounted on the substrate and including a plurality of pads arranged in line in a first direction, the pads including a first power supply pad;   an additional conductive layer formed over the semiconductor chip so that the additional conductive layer is on a side opposite to the substrate, the additional conductive layer being vertically away from and electrically coupled to the first power supply pad of the semiconductor chip; and   a first power supply path elongated in the first direction and connecting the first power supply terminal of the substrate to the additional conductive layer to convey the first power supply voltage to the first power supply pad with an intervention of the additional conductive layer.   
     
     
         17 . The device as claimed in  claim 16 , wherein the first power supply path includes a bonding wiring. 
     
     
         18 . The device as claimed in  claim 16 , wherein the substrate includes a second power supply terminal configured to be supplied with a second power supply voltage, and the pads of the semiconductor chip includes a second power supply pad, and the device further comprises a second power supply path elongated in a second direction, that is substantially perpendicular to the first direction, and connecting the second power supply terminal of the substrate to the second power supply pad of the semiconductor chip to convey the second power supply voltage to the second power supply pad. 
     
     
         19 . The device as claimed in  claim 18 , wherein the first power supply path includes a fist bonding wiring and the second power supply path includes a second bonding wiring.