US2013161814A1PendingUtilityA1

Semiconductor chip with offset pads

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Assignee: SU MICHAEL ZPriority: Aug 14, 2010Filed: Feb 22, 2013Published: Jun 27, 2013
Est. expiryAug 14, 2030(~4.1 yrs left)· nominal 20-yr term from priority
Inventors:Michael Z. SuGamal Refai-AhmedBryan Black
H10W 74/15H10W 90/722H10W 90/734H10W 90/724H10W 72/01255H10W 72/01235H10W 72/01223H10W 72/251H10W 72/248H10W 72/241H10W 72/227H10W 72/222H10W 72/072H10W 90/701H10W 72/20H10W 70/635H10W 70/69H10W 90/00H10W 72/237H10W 72/234H10W 72/07253H01L 23/49811
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Claims

Abstract

A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus, comprising:
 a first semiconductor chip adapted to be stacked with a second semiconductor chip, the second semiconductor chip including a side and first and second conductor structures projecting from the side; and   the first semiconductor chip including a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and having a first lateral dimension and being adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.   
     
     
         2 . The apparatus of  claim 1 , wherein the first semiconductor chip comprises an interposer. 
     
     
         3 . The apparatus of  claim 1 , comprising a solder structure positioned each of the first and second conductor pillars. 
     
     
         4 . The apparatus of  claim 1 , comprising the second semiconductor chip stacked with the first semiconductor chip wherein the first conductor structure is coupled to the first conductor pillar and the second conductor structure is coupled to the second conductor pillar. 
     
     
         5 . The apparatus of  claim 4 , wherein the first and second conductor structures comprise conductor pillars. 
     
     
         6 . The apparatus of  claim 5 , comprising a solder structure positioned on an end of each of the conductor pillars. 
     
     
         7 . The apparatus of  claim 1 , comprising a circuit board coupled to the first semiconductor chip. 
     
     
         8 . The apparatus of  claim 7 , wherein the circuit board comprises a semiconductor chip package substrate. 
     
     
         9 . An apparatus, comprising:
 a first semiconductor chip adapted to be stacked with a second semiconductor chip, the second semiconductor chip including a side and first and second conductor structures projecting from the side; and   the first semiconductor chip including a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and having a first lateral dimension and being adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad toward the first edge and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.   
     
     
         10 . The apparatus of  claim 9 , wherein the first semiconductor chip comprises an interposer. 
     
     
         11 . The apparatus of  claim 9 , comprising a solder structure positioned each of the first and second conductor pillars. 
     
     
         12 . The apparatus of  claim 9 , comprising the second semiconductor chip stacked with the first semiconductor chip wherein the first conductor structure is coupled to the first conductor pillar and the second conductor structure is coupled to the second conductor pillar. 
     
     
         13 . The apparatus of  claim 12 , wherein the first and second conductor structures comprise conductor pillars. 
     
     
         14 . The apparatus of  claim 13 , comprising a solder structure positioned on an end of each of the conductor pillars. 
     
     
         15 . The apparatus of  claim 9 , comprising a circuit board coupled to the first semiconductor chip. 
     
     
         16 . The apparatus of  claim 15 , wherein the circuit board comprises a semiconductor chip package substrate. 
     
     
         17 . An apparatus, comprising:
 a first semiconductor chip adapted to be stacked with a second semiconductor chip, the second semiconductor chip including a side and first and second conductor structures projecting from the side; and   the first semiconductor chip including a first corner, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first corner and having a first lateral dimension and being adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first corner than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.   
     
     
         18 . The apparatus of  claim 17 , wherein the first semiconductor chip comprises an interposer. 
     
     
         19 . The apparatus of  claim 17 , comprising a solder structure positioned each of the first and second conductor pillars. 
     
     
         20 . The apparatus of  claim 17 , comprising the second semiconductor chip stacked with the first semiconductor chip wherein the first conductor structure is coupled to the first conductor pillar and the second conductor structure is coupled to the second conductor pillar.

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