Strained channel for depleted channel semiconductor devices

Abstract

A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

1 . A method of fabricating a semiconductor device comprising:
 providing a replacement gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, wherein the SOI layer has a first thickness of less than 15 nm.   forming raised source and drain regions on opposing sides of the replacement gate structure;   removing the replacement gate structure to expose the channel portion of the SOI layer of the SOI substrate;   etching the channel portion of the SOI layer to a second thickness that is less than the first thickness;   depositing an epitaxially grown semiconductor layer on the channel portion of the SOI layer having the second thickness, wherein a lattice dimension of the epitaxially grown semiconductor layer is different than a lattice dimension of the channel portion of the SOI layer to provide a strained channel; and   forming a functional gate structure on the strained channel.   
     
     
         2 . The method of  claim 1 , wherein the SOI layer has a first thickness that ranges from 2 nm to 10 nm. 
     
     
         3 . The method of  claim 1 , wherein the forming of the raised source and drain regions on opposing sides of the replacement gate structure comprises epitaxial growth of an in-situ doped semiconductor material. 
     
     
         4 . The method of  claim 1 , wherein the removing of the replacement gate structure to expose the channel portion of the SOI layer of the SOI substrate comprises selective etching, wherein the selective etching removes the material of the replacement gate structure selectively to the raised source and drain regions and the channel portion of the SOI layer. 
     
     
         5 . The method of  claim 1  further comprising forming dielectric spacers on sidewalls of the raised source and drain regions that are exposed by removing the replacement gate structure. 
     
     
         6 . The method of  claim 1 , wherein the etching of the channel portion of the SOI layer comprises a halide gas comprising a hydrogen chloride (HCl) gas, a chlorine (Cl 2 ) gas or a combination thereof. 
     
     
         7 . The method of  claim 1 , wherein the second thickness of the channel portion of the SOI layer ranges from 1.0 nm to 5.0 nm, and the epitaxially grown semiconductor layer has a thickness that ranges from 1.0 nm to 5.0 nm. 
     
     
         8 . The method of  claim 1 , wherein the raised source and drain regions are doped to a p-type conductivity, the channel portion of the SOI layer having the second thickness is silicon, and the epitaxially grown semiconductor layer is silicon germanium (SiGe), or the raised source and drain regions are doped to an n-type conductivity, the channel portion of the SOI layer having the second thickness is silicon, and the epitaxially grown semiconductor layer is silicon doped with carbon (Si:C). 
     
     
         9 - 25 . (canceled)