Low external resistance etsoi transistors

Abstract

A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.

1 . A semiconductor structure comprising:
 a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, a buried insulator layer, and a top semiconductor layer;   a U-shaped gate dielectric comprising a high dielectric constant (high-k) material including a dielectric metal oxide and having a dielectric constant greater than 3.9 and having a bottommost surface that is in contact with a first portion of a topmost surface of said top semiconductor layer;   a raised source region in contact with a second portion of said topmost surface of said top semiconductor layer and with said high-k material at a lower portion of a first outer sidewall of said U-shaped gate dielectric;   a raised drain region in contact with a third portion of said topmost surface of said top semiconductor layer and with said high-k material at a lower portion of a second outer sidewall of said U-shaped gate dielectric; and   a dielectric gate spacer laterally contacting upper portions of said first and second outer sidewalls of said U-shaped gate dielectric.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein an interface between said raised source region and said dielectric gate spacer is coplanar with an interface between said raised drain region and said dielectric gate spacer. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising:
 at least one work function metallic layer contacting inner surfaces of said U-shaped gate dielectric; and   a gate conductor portion contacting inner surfaces of said at least one work function metallic layer.   
     
     
         4 . The semiconductor structure of  claim 1 , further comprising:
 a planar source region located within said top semiconductor layer and contacting a bottom surface of said raised source region; and   a planar drain region located with said top semiconductor layer and contacting a bottom surface of said raised drain region.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein said raised source region and said raised drain region have electrical dopants at a greater atomic concentration than said planar source region and said planar drain region. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 a source-side metal semiconductor alloy portion contacting a top surface of said raised source region and having a top surface that is above a plane of a bottom surface of said dielectric gate spacer; and   a drain-side metal semiconductor alloy portion contacting a top surface of said raised drain region and having a top surface that is above said plane of said bottom surface of said dielectric gate spacer.   
     
     
         7 . The semiconductor structure of  claim 6 , wherein a bottom surface of said raised source region and a bottom surface of said raised drain region are located below said plane of said bottom surface of said dielectric gate spacer. 
     
     
         8 . The semiconductor structure of  claim 6 , wherein said source-side metal semiconductor alloy portion is in contact with outer sidewalls of said dielectric gate spacer. 
     
     
         9 . The semiconductor structure of  claim 6 , further comprising an outer dielectric gate spacer laterally contacting outer sidewalls of said dielectric gate spacer, overlying portions of said raised source region and said raised drain region, and contacting said source-side metal semiconductor alloy portion and said drain-side metal semiconductor alloy portion. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein a bottommost surface of said dielectric gate spacer is vertically spaced from a topmost surface of said top semiconductor layer by a portion of said raised source region or a portion of said raised drain region. 
     
     
         11 . The semiconductor structure of  claim 1 , wherein a thickness of portions of said raised source region and said drain region underlying said dielectric gate spacer is greater than a thickness of said top semiconductor layer. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein a topmost surface of said U-shaped gate dielectric is coplanar with a top surface of said dielectric gate spacer. 
     
     
         13 . The semiconductor structure of  claim 1 , wherein said top semiconductor layer comprises a first semiconductor material, said raised source region and said raised drain region comprise a second semiconductor material that is different from said first semiconductor material. 
     
     
         14 . The semiconductor structure of  claim 1 , wherein said raised source region and said raised drain region comprise a single crystalline semiconductor material that is epitaxially aligned to another single crystalline material located within said top semiconductor layer. 
     
     
         15 . The semiconductor structure of  claim 1 , wherein a bottommost surface of said U-shaped gate dielectric is coplanar with bottom surfaces of said raised source region and raised drain region. 
     
     
         16 .- 25 . (canceled)