Methods for deposition of tungsten in the fabrication of an integrated circuit

Abstract

A method for fabricating an integrated circuit includes providing a semiconductor wafer comprising a hole etched therein, depositing a first layer comprising tungsten onto the semiconductor wafer and into the hole therein, thereby filling the hole with the first layer, and etching the first layer from the semiconductor wafer, wherein etching the first layer results in the formation of a divot above the first layer within the hole. The method may further include depositing a second layer comprising tungsten onto the semiconductor wafer and into the divot formed above the first layer within the hole and polishing the second layer from the semiconductor wafer, wherein polishing the second layer does not remove the second layer deposited into the divot.

What is claimed is: 
     
         1 . A method for fabricating an integrated circuit, the method comprising:
 providing a semiconductor wafer comprising a hole etched therein, the hole having a substantially constant diameter along its entire length;   depositing a first layer comprising tungsten onto the semiconductor wafer and into the hole therein, thereby completely filling the entire hole with the first layer, wherein depositing the first layer comprising tungsten is performed at a first tungsten deposition rate with first precursor materials;   etching the first layer from the semiconductor wafer, wherein etching the first layer removes a portion of the first layer from within an upper portion of the hole, thereby resulting in the formation of a divot above a remaining portion of the first layer within a lower portion of the hole;   depositing a second layer comprising tungsten onto the semiconductor wafer and into the divot formed above the first layer within the upper portion of the hole so as to completely fill the upper portion of the hole, wherein depositing the second layer comprising tungsten is performed at a second tungsten deposition rate that is faster than the first tungsten deposition rate with second precursor materials that differ from the first precursor materials;   polishing, in a first polishing step, the second layer from the semiconductor wafer so as to remove the second layer from portions of the semiconductor wafer that are above the hole; and   polishing, in a second polishing step performed subsequent to the first polishing step, the semiconductor wafer with a CMP slurry that does not electrochemically interact with a remaining portion of the second layer that remains in the divot subsequent to the first polishing step, wherein the second polishing step does not remove the remaining portion of the second layer deposited into the divot.   
     
     
         2 . The method of  claim 1 , wherein providing the semiconductor wafer comprises providing a semiconductor wafer comprising the hole formed through a single TEOS layer. 
     
     
         3 . The method of  claim 1 , wherein providing the semiconductor wafer comprising a hole etched therein comprises providing a semiconductor wafer with a contact hole or a via hole etched therein. 
     
     
         4 . The method of  claim 1 , further comprising depositing a protective metal layer onto the semiconductor wafer prior to depositing the first layer. 
     
     
         5 . The method of  claim 4 , wherein depositing the protective metal layer comprises depositing a TiN layer. 
     
     
         6 . The method of  claim 4 , wherein depositing the protective metal layer comprises depositing a Ti, Ta, or TaN layer. 
     
     
         7 . The method of  claim 1 , wherein depositing the first layer comprises a chemical vapor deposition procedure. 
     
     
         8 . The method of  claim 1 , wherein depositing the second layer comprises a chemical vapor deposition procedure. 
     
     
         9 . (canceled) 
     
     
         10 . The method of  claim 2 , wherein depositing the first layer comprising tungsten comprises depositing W from WF 6  with a precursor comprising a first amount of B. 
     
     
         11 . (canceled) 
     
     
         12 . The method of  claim 10 , wherein depositing the second layer comprising tungsten comprises depositing W from WF 6  with a precursor comprising Si and a second amount of B that is less than the first amount of B. 
     
     
         13 . The method of  claim 1 , wherein etching the first layer comprises a wet etch procedure. 
     
     
         14 . The method of  claim 1 , wherein polishing the second layer comprises a chemical mechanical planarization procedure. 
     
     
         15 . The method of  claim 1 , wherein depositing the first layer comprises depositing the first layer to a thickness from about 200 Å to about 800 Å above the hole. 
     
     
         16 . The method of  claim 1 , further comprising depositing an ILD layer after polishing the second layer. 
     
     
         17 . The method of  claim 16 , further comprising etching the ILD layer after depositing the ILD layer. 
     
     
         18 . The method of  claim 17 , wherein etching the ILD layer comprises etching the ILD layer above the hole to a depth sufficient for contact with the second layer deposited in the divot. 
     
     
         19 . (canceled) 
     
     
         20 . (canceled) 
     
     
         21 . The method of  claim 12 , wherein the second layer comprising tungsten has a texture and an electronic potential that differs from a texture and an electronic potential of the first layer comprising tungsten, and wherein the texture and electronic potential of the second layer comprising tungsten prevents electrochemical transport between the second layer comprising tungsten and the CMP slurry used in the second polishing step.