Field effect transistors including fin structures with different doped regions and semiconductor devices including the same

Abstract

Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fm portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.

What is claimed is: 
     
         1 . A Field Effect Transistor (FET) structure, comprising:
 a device isolation layer on a substrate; and   a fin extending from the substrate to protrude from the device isolation layer, the fin comprising a threshold voltage control region of the FET structure being doped with a first concentration of impurities and a carrier region of the FET structure on the threshold voltage control region being doped with a second concentration of impurities that is less than the first concentration of impurities.   
     
     
         2 . The structure of  claim 1  wherein a total width of the fin including the threshold voltage control region and the carrier region is greater than about 10 nm; and
 wherein the threshold voltage control region comprises an inner portion of the fin and the carrier region comprises an outer portion of the fin grown on the inner portion. 
 
     
     
         3 . The structure of  claim 1  wherein a total width of the fin including the threshold voltage control region and the carrier region is greater than about an amount where volume inversion occurs in the fin; and
 wherein the threshold voltage control region comprises an inner portion of the fin and the carrier region comprises an outer portion of the fin grown on the inner portion. 
 
     
     
         4 . The structure of  claim 2  wherein the second concentration of impurities comprises diffused impurities from the first concentration of impurities. 
     
     
         5 . The structure of  claim 2  wherein the second concentration of impurities comprises about 10 percent or less of the first concentration of impurities. 
     
     
         6 . The structure of  claim 1  wherein a total width of the fin including the threshold voltage control region and the carrier region is less than about 10 nm; and
 wherein the carrier region comprises an inner portion of the fin and the threshold voltage control region comprises an outer portion of the fin grown on the inner portion. 
 
     
     
         7 . The structure of  claim 1  wherein a total width of the fin including the threshold voltage control region and the carrier region is less than an amount where volume inversion occurs in the fin; and
 wherein the carrier region comprises an inner portion of the fin and the threshold voltage control region comprises an outer portion of the fm grown on the inner portion. 
 
     
     
         8 . The structure of  claim 6  wherein the second concentration of impurities comprises diffused impurities from the first concentration of impurities. 
     
     
         9 . The structure of  claim 6  wherein the second concentration of impurities comprises about 10 percent or less of the first concentration of impurities. 
     
     
         10 . A Field Effect Transistor (FET) structure, comprising:
 a device isolation layer on a substrate;   a fin including:
 an inner portion of the fin extending from the substrate to protrude from the device isolation layer to provide upper side walls and a top surface, the inner portion of the fin being doped with a first concentration of impurities to provide a threshold voltage control region; and 
 an outer portion of the fin, on the inner portion, comprising a semiconductor layer grown on the top surface and on the upper side walls of the inner portion of the fin, the semiconductor layer being doped with a second concentration of impurities that is less than the first concentration of impurities to provide a carrier region; and 
 a gate structure crossing over the fin. 
   
     
     
         11 . The structure of  claim 10  wherein the semiconductor layer comprises an un-doped semiconductor layer. 
     
     
         12 . The structure of  claim 10  wherein the second concentration of impurities comprises diffused impurities from the inner portion of the fin including the first concentration of impurities. 
     
     
         13 . The structure of  claim 10  wherein the second concentration of impurities comprises about 10 percent or less of the first concentration of impurities. 
     
     
         14 . The structure of  claim 13  wherein the semiconductor layer further comprises additional impurities diffused from the inner portion of the fin. 
     
     
         15 . The structure of  claim 10  wherein the gate structure comprises:
 a gate electrode comprising doped polysilicon and/or metal; and 
 a gate dielectric layer comprising a high K dielectric material, on the gate electrode. 
 
     
     
         16 . The structure of  claim 10  wherein a total width of the fin including the threshold voltage control region and the carrier region is greater than about an amount where volume inversion occurs in the fin. 
     
     
         17 . The structure of  claim 16  wherein the total width is about 10 nm. 
     
     
         18 . The structure of  claim 10  further comprising:
 raised source/drain regions adjacent to the fin, the raised source/drain regions comprising a lattice constant that is different than respective lattice constants of the inner and outer portions of the fin. 
 
     
     
         19 . A semiconductor device comprising;
 a device isolation layer on a substrate;   a first transistor including a first semiconductor structure protruding from the device isolation layer including a first semiconductor layer providing a first channel during operation of the first transistor and including a first threshold voltage control region doped heavier than the first semiconductor layer to provide a first threshold voltage;   a first gate electrode and a first gate dielectric crossing over the first semiconductor structure;   a second transistor including a second semiconductor structure protruding from the device isolation layer including a second semiconductor layer providing a second channel during operation of the second transistor and including a second threshold voltage control region doped heavier than the second semiconductor layer to provide a second first threshold voltage; and   a second gate electrode and a second gate dielectric crossing over the second semiconductor structure; and   wherein the first and second threshold voltages comprise different threshold voltages.   
     
     
         20 . The device of  claim 19  wherein a total width of the first semiconductor structure including the first threshold voltage control region and the first semiconductor layer is greater than about an amount where volume inversion occurs in the first semiconductor structure; and
 wherein the first threshold voltage control region comprises an inner portion of the first semiconductor structure and the first semiconductor layer comprises an outer portion of the first semiconductor structure grown on the inner portion. 
 
     
     
         21 . The device of  claim 19  wherein a total width of the first semiconductor structure including the first threshold voltage control region and the first semiconductor layer is less than about an amount where volume inversion occurs in the first semiconductor structure; and
 wherein the first semiconductor layer comprises an inner portion of the first semiconductor structure and the first threshold voltage control region comprises an outer portion of the first semiconductor structure grown on the inner portion. 
 
     
     
         22 . The structure of  claim 19  wherein the substrate comprises a silicon-on-insulator substrate. 
     
     
         23 . A Field Effect Transistor (FET) structure, comprising:
 a device isolation layer on a substrate;   a fin comprising a total width less than about 10 nm, including:
 an inner portion of the fin extending from the substrate to protrude from the device isolation layer to provide upper side walls, a top surface, and a channel region, the inner portion of the fin being doped with a first concentration of impurities; 
 an outer portion of the fin comprising a semiconductor layer grown on the top surface and on the upper side walls of the inner portion of the fin, the semiconductor layer being doped with a second concentration of impurities that is greater than the first concentration of impurities; and 
   a gate structure crossing over the fin opposite the channel region.   
     
     
         24 . The structure of  claim 23  wherein the inner portion comprises a carrier region of the fin and the outer portion comprises a threshold voltage control region. 
     
     
         25 . The structure of  claim 23  wherein the first concentration of impurities comprises diffused impurities from the second concentration of impurities. 
     
     
         26 . The structure of  claim 23  wherein the first concentration of impurities comprises about 10 percent or less of the second concentration of impurities. 
     
     
         27 . The structure of  claim 23  further comprising:
 raised source/drain regions adjacent to the fin, the raised source/drain regions comprising a lattice constant that is different than respective lattice constants of the inner and outer portions of the fin. 
 
     
     
         28 . An integrated circuit device comprising a plurality of Field Effect Transistor (FET) structures, comprising:
 a device isolation layer on a substrate;   a first FET structure including a plurality of first fins extending from the substrate to protrude from the device isolation layer, the first fins each comprising a threshold voltage control region of the first FET structure being doped with a first concentration of impurities and a carrier region of the first FET structure on the threshold voltage control region being doped with a second concentration of impurities that is less than the first concentration of impurities; and   a gate structure crossing over the plurality of first fins.   
     
     
         29 . The device of  claim 28  further comprising:
 a second FET structure, spaced apart from the first FET structure, including a single fin extending from the substrate to protrude from the device isolation layer, the single fin comprising a threshold voltage control region of the second FET structure being doped with the first concentration of impurities and a carrier region of the second FET structure on the threshold voltage control region being doped with the second concentration of impurities, the gate structure crossing over the single fin. 
 
     
     
         30 . The device of  claim 28  further comprising:
 a second FET structure, spaced apart from the first FET structure, including a plurality of second fins extending from the substrate to protrude from the device isolation layer, the second fins each comprising a threshold voltage control region of the second FET structure being doped with the first concentration of impurities and a carrier region of the second FET structure on the threshold voltage control region being doped with the second concentration of impurities, the gate structure crossing over the plurality of second fins, 
 wherein a first number of fins included in the plurality of first fins is different than a second number of fins included in the plurality of second fins. 
 
     
     
         31 . The device of  claim 28  wherein respective total widths of the first fins are greater than about an amount where volume inversion occurs in the first fins;
 wherein each of the threshold voltage control regions comprises a respective inner portion of the first fins and each of the carrier regions comprises a respective outer portion of the first fins, grown on the inner portions. 
 
     
     
         32 . The device of  claim 31  wherein the second concentration of impurities comprises about 10 percent or less of the first concentration of impurities. 
     
     
         33 . The device of  claim 26  wherein respective total widths of the first fins are less than an amount where volume inversion occurs in the first fins; and
 wherein each of the carrier regions comprises a respective inner portion of the first fins and each of the threshold voltage control regions comprises a respective outer portion of the first fins, grown on the inner portions. 
 
     
     
         34 . The device of  claim 33  wherein the second concentration of impurities comprises diffused impurities from the first concentration of impurities. 
     
     
         35 . The device of  claim 33  wherein the second concentration of impurities comprises about 10 percent or less of the first concentration of impurities. 
     
     
         36 . A Field Effect Transistor (FET) structure, comprising:
 a device isolation layer on a substrate; and   an active semiconductor layer extending from the substrate to protrude from the device isolation layer, the active semiconductor layer comprising a threshold voltage control region of the FET structure being doped with a first concentration of impurities and a carrier region of the FET structure on the threshold voltage control region being doped with a second concentration of impurities that is less than the first concentration of impurities.   
     
     
         37 . The structure of  claim 36  wherein the active semiconductor layer comprises an omega shaped silicon structure including upper side walls and a neck portion that is narrower than a width of the omega shaped silicon structure across the upper side walls. 
     
     
         38 . The structure of  claim 36  wherein the active semiconductor layer comprises a gate-all-around structure. 
     
     
         39 . The structure of  claim 38  wherein the gate-all-around structure comprises a nanowire structure comprising a width less than about 10 nm.