US2013299868A1PendingUtilityA1

Dry flux bonding device and method

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Assignee: MICRON TECHNOLOGY INCPriority: May 25, 2010Filed: Jul 17, 2013Published: Nov 14, 2013
Est. expiryMay 25, 2030(~3.8 yrs left)· nominal 20-yr term from priority
Inventors:Owen R. FayXiao LiJosh D. WoodlandShijian LuoJaspreet S. GandhiTe-Sung Wu
H10W 72/0198H10W 72/07336H10W 72/073H10W 72/30H10H 20/01H10H 20/018H10H 20/857H01L 33/62
49
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Claims

Abstract

Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor wafer, comprising:
 at least one LED formed on the semiconductor wafer;   at least one electrical conduction surface coupled to the LED;   a layer of nickel formed over the electrical conduction surface;   a tin containing layer formed over the electrical conduction surface; and   a fluorinated compound layer including tin and fluorine formed over the tin containing layer.   
     
     
         2 . The semiconductor wafer of  claim 1 , wherein the tin containing layer includes silver. 
     
     
         3 . The semiconductor wafer of  claim 1 , wherein the fluorinated compound layer includes tin and fluorine and oxygen. 
     
     
         4 . The semiconductor wafer of  claim 1 , further including a barrier material between the electrical conduction surface and the layer of nickel. 
     
     
         5 . The semiconductor wafer of  claim 4 , wherein the barrier material includes titanium. 
     
     
         6 . The semiconductor wafer of  claim 5 , wherein the barrier material includes tungsten. 
     
     
         7 . A semiconductor wafer, comprising:
 at least one LED formed on the semiconductor wafer;   at least one electrical conduction surface coupled to the LED;   a layer of copper formed over the electrical conduction surface;   a tin containing layer formed over the electrical conduction surface; and   a fluorinated compound layer including tin and fluorine formed over the tin containing layer.   
     
     
         8 . The semiconductor wafer of  claim 7 , wherein the tin containing layer includes silver. 
     
     
         9 . A semiconductor wafer, comprising:
 at least one LED formed on the semiconductor wafer;   at least one electrical conduction surface coupled to the LED;   a noble metal layer formed over the electrical conduction surface;   a tin containing layer formed over the electrical conduction surface; and   a fluorinated compound layer including tin and fluorine formed over the tin containing layer.   
     
     
         10 . The semiconductor wafer of  claim 9 , wherein the noble metal layer includes gold. 
     
     
         11 . The semiconductor wafer of  claim 9 , wherein the noble metal layer includes platinum. 
     
     
         12 . A semiconductor wafer, comprising:
 at least one LED formed on the semiconductor wafer;   at least one electrical conduction surface coupled to the LED;   a first metallic region formed over the electrical conduction surface;   a second metallic region formed over the first metallic region; and   a metal oxide greater than a native oxide formed over the second metallic region.   
     
     
         13 . The semiconductor wafer of  claim 12 , wherein the first metallic region includes nickel. 
     
     
         14 . The semiconductor wafer of  claim 13 , wherein the second metallic region includes tin. 
     
     
         15 . The semiconductor wafer of  claim 14 , wherein the first metallic region is formed as a layer having a first thickness, and the second metallic region is formed as a layer having a second thickness, and a ratio of the first thickness to the second thickness is not greater than 3.5 to 1. 
     
     
         16 . The semiconductor wafer of  claim 15 , wherein the ratio of the first thickness to the second thickness is approximately 1 to 1. 
     
     
         17 . The semiconductor wafer of  claim 12 , further including a barrier material between the electrical conduction surface and the first metallic region. 
     
     
         18 . The semiconductor wafer of  claim 17 , wherein the barrier material includes titanium. 
     
     
         19 . The semiconductor wafer of  claim 17 , wherein the barrier material includes tungsten.

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