Method for forming integrated circuit structure with capacitor and resistor and method for forming

Abstract

An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.

What is claimed is: 
     
         1 . A method of fabricating an integrated circuit, comprising;
 depositing a metallic material;   depositing a conductive etch stop material on top of said metallic material;   depositing a dielectric on top of said conductive etch stop material;   depositing a top plate material on said dielectric;   forming a first photoresist pattern over said top plate material to define a top plate of a capacitor;   etching away portions of said top plate material and said dielectric exposed by said first photoresist pattern and stopping in said conductive etch stop material.   forming a second photoresist pattern to define a bottom plate of said capacitor and to define a metallic device; and   etching away portions exposed said etch stop material and said metallic material exposed by said second photoresist pattern to form said bottom plate of the capacitor and said metallic device.   
     
     
         2 . The method of  claim 1  wherein said metallic device is a resistor and said metallic material is selected from the group consisting of TiAl, Ti, TiN, Ta, TaN, Ir/TiAlN, Ir, TiAlN, SiCr, NiCr, and TiWN. 
     
     
         3 . The method of  claim 1  wherein said conductive etch stop material is selected from the group consisting of TiAlON, TiAlN, and TiAlO. 
     
     
         4 . The method of  claim 3  wherein said conductive etch stop material has a resistivity about 10 times greater than said metallic material. 
     
     
         5 . The method of  claim 1  where said metallic material is composed of TiAl with a Ti to Al atomic ratio between 80:20 and 50:50 and where conductive etch stop material is TiAlON where Ti to Al ratio in said TiAlON is within 20% of said Ti to Al ratio in said metallic material and where a Ti plus Al atomic concentration in said TiAlON is approximately equal to a O+N atomic concentration and where a N to O ratio is between 95:5 and 60:40. 
     
     
         6 . The method of  claim 1  wherein said capacitor is an FRAM memory cell. 
     
     
         7 . The method of  claim 1  wherein said metallic device is a local interconnect and said first metallic material is selected from the group consisting of TiAl, W, TiW, Ti, Ta, and TaN. 
     
     
         8 . The method of  claim 1  wherein said metallic device is an electrically programmable fuse and said first metallic material is selected from the group consisting of TiN, TaN, TiW, TiAlN, and TiAlO.